Abstract: System and method for generating a Network on Chip (NoC) includes intaking a specification, where the specification includes, for each sub-NoC design, hierarchical topology and Control/Status Register (CSR) controllers of the each sub-NoC with locations thereof. Further, for each of the CSR controller in the sub-NoC, the sub-NoC design includes a set of CSR endpoints that is communicatively coupled to the each of the CSR controllers and ingress and egress points of a boundary of the each sub-NoC. The network definition is generated for the each sub-NoC design from computation of routes between the locations of each pair of the CSR controllers and the set of CSR endpoints that communicate via a routing graph defined from the hierarchical topology that is adjusted based on the ingress and egress points. NoCs may be generated based on the network definitions.

Abstract: System and method for generating a Network on Chip (NoC) includes intaking a specification, where the specification includes, for each sub-NoC design, hierarchical topology and Control/Status Register (CSR) controllers of the each sub-NoC with locations thereof. Further, for each of the CSR controller in the sub-NoC, the sub-NoC design includes a set of CSR endpoints that is communicatively coupled to the each of the CSR controllers and ingress and egress points of a boundary of the each sub-NoC. The network definition is generated for the each sub-NoC design from computation of routes between the locations of each pair of the CSR controllers and the set of CSR endpoints that communicate via a routing graph defined from the hierarchical topology that is adjusted based on the ingress and egress points. NoCs may be generated based on the network definitions.

Abstract: A Network on Chip (NoC) includes a plurality of shared buffers configured to manage arriving flits with a plurality of logical queues, each of the plurality of logical queues configured to manage the arriving flits according to a virtual channel of an input port associated with the arriving flits and an output port corresponding to the arriving flits. A first set of arbitration logic is configured to output arbitration of flits from the plurality of logical queues to a second set of arbitration logic. The second set of arbitration logic is configured to arbitrate output flits from the first set of arbitration logic to the output port. Additionally, the configuration of the shared buffers with two-set of arbitration logic provides efficient arbitration of data transmission.

Abstract: A method for generating a Network on Chip (NoC) that includes computing a virtual channel (VC) mapping that associates each flow of the NoC with a split VC identifier, the split VC identifier including a host VC identifier and a discriminant and generating the NoC comprising multiply instantiated routers, wherein a design of each of the multiply instantiated routers is configured with allocated VC identifiers according to the VC mapping. Further, the method includes remapping the VC identifiers for each of the multiply instantiated routers based on its connection to other ones of the multiply instantiated routers and where allocation of VC identifiers is conducted according to each slice of the design of the multiply instantiated routers. Using split VC identifiers allows the multiply instantiated routers to have VC remapping/transformation functions that enable desired VC remapping at a plurality of positions on the NoC.

Abstract: A method for load balancing flows of a Network on Chip (NoC) having a plurality of routers and a plurality of bridges arranged into a plurality of clusters described herein includes receiving packets at the NoC, the packet being associated with a target destination as specified by a cluster identifier and a local identifier. For receipt of each packet, the method includes routing the packet to a destination in the NoC according to the local identifier for the NoC having a same cluster identifier as the cluster identifier associated with the packet, and routing the packet according to a route lookup from referencing the cluster identifier and a path identifier associated with the packet for the NoC having a different cluster identifier from the cluster identifier associated with the packet.

Abstract: Aspects of the present disclosure are directed to a method and a system for mapping flows of a Network-on-Chip (NoC). The method includes identifying hierarchically distinct flows across a plurality of instances of a sub-NoC, determining a unified route and Virtual Channel (VC) for each of the hierarchically distinct flows, and projecting the unified route and VC back to flow instances in each of the plurality of instances of the sub-NoC. By determining the unified route and VC for hierarchically distinct flows corresponding to flow instances of different instances of a sub-NoC, the method minimizes redundancy of mapping determination, and of resources during elaboration of NoC components.

Abstract: System and methods for automatically generating control/status registers (CSR) based on configurations of components in a Network on Chip (NoC) include generating at least one repeatable field group from a plurality of defined fields, each of the plurality of defined fields defining portions of a register and NoC connectivity, generating at least one repeatable multi-register from the at least one repeatable field group, and generating at least one CSR group from the at least one repeatable multi-register, the at least one CSR group generated to be incorporated into a CSR bank. Such systems and methods of generating CSRs provides flexibility for designers/users to optimize the NoC for area consumption, reducing cost and complexity, parameterize configurations of the CSRs, and the like.

Abstract: Apparatus and methods for constructing Network on Chips (NoCs) by algorithmically elaborating one or more of Network on Chips (NoCs) through a hierarchical topology composed of instantiations of sub-NoCs and leaf components, and one or more connectivity definitions. Designing NoCs using one or more instantiations of sub-NoCs reduces overheads during chip backend processes, such as for timing closure.

Abstract: Systems and methods include a control layer and a Network on Chip (NoC). The NoC includes a plurality of routers interconnected with both packet transport wires and global support wires. The global support wires are specifically configured to distribute wired signal inputs to processing functions of the plurality of routers, as determined by the control layer. This configuration enables the control layer to effectively configure the processing functions of each router, thereby enhancing the efficiency and adaptability of the NoC to meet different operational demands.

Abstract: Method for transporting packets in a multi-cluster Network on Chip (NoC) interconnect with a transport protocol significantly enhance packet management in complex NoC chip architectures. This approach involves processing a packet within clusters to determine a destination cluster and a destination node, and executing a node lookup for the packet intended for different clusters. This lookup identifies an optimal path for transporting the packet out of the cluster. The multi-cluster NoC interconnect efficiently outlines cluster-to-cluster connections and manages global traffic, incorporating deadlock prevention techniques. Global bridges and boundary bridges facilitate effective traffic management between clusters. Each node includes a programmable path table that dynamically assigns efficient routes. This method significantly improves packet management across multi-cluster NoCs, offering a scalable, efficient, and reliable solution for complex computing environments.

Abstract: A method for load balancing flows of a Network on Chip (NoC) having a plurality of routers and a plurality of bridges arranged into a plurality of clusters described herein includes receiving packets at the NoC, the packet being associated with a target destination as specified by a cluster identifier and a local identifier. For receipt of each packet, the method includes routing the packet to a destination in the NoC according to the local identifier for the NoC having a same cluster identifier as the cluster identifier associated with the packet, and routing the packet according to a route lookup from referencing the cluster identifier and a path identifier associated with the packet for the NoC having a different cluster identifier from the cluster identifier associated with the packet.

Abstract: Systems and methods described herein are directed to solutions for Network on Chip (NoC) interconnects that automatically and dynamically determines the position of hosts of various size and shape in a NoC topology based on the connectivity, bandwidth and latency requirements of the system traffic flows and certain performance optimization metrics such as system interconnect latency and interconnect cost. The example embodiments selects hosts for relocation consideration and determines a new possible position for them in the NoC based on the system traffic specification, shape and size of the hosts and by using probabilistic function to decide if the relocation is carried out or not. The procedure is repeated over new sets of hosts until certain optimization targets are satisfied or repetition count is exceeded.

Abstract: Methods, systems, and non-transitory computer readable medium for automatically characterizing performance of a System-on-Chip (SoC) and/or Network-on-Chip (NoC) with respect to latency and throughput attributes of one or more traffic flows/profiles under varying traffic load conditions. The characterization of performance may involve a plot representative of latency and throughput, depending on the desired implementation.

Abstract: The present disclosure is directed to buffer sizing of NoC link buffers by utilizing incremental dynamic optimization and machine learning. A method for configuring buffer depths associated with one or more network on chip (NoC) is disclosed. The method includes deriving characteristics of buffers associated with the one or more NoC, determining first buffer depths of the buffers based on the characteristics derived, obtaining traces based on the characteristics derived, measuring trace skews based on the traces obtained, determining second buffer depths based on the trace skews measured, optimizing the buffer depths associated with the network on chip (NoC) based on the second buffer depths, and configuring the buffer depths associated with one or more network on chip (NoC) based on the buffer depths optimized.

Abstract: Systems and methods for performing multi-message transaction based performance simulations of SoC IP cores within a Network on Chip (NoC) interconnect architecture by accurately imitating full SoC behavior are described. The example implementations involve simulations to evaluate and detect NoC behavior based on execution of multiple transactions at different rates/times/intervals, wherein each transaction can contain one or more messages, with each message being associated with a source agent and a destination agent. Each message can also be associated with multiple parameters such as rate, size, value, latency, among other like parameters that can be configured to indicate the execution of the transaction by a simulator to simulate a real-time scenario for generating performance reports for the NoC interconnect.

Abstract: Example implementations as described herein are directed to systems and methods for processing a NoC specification for a plurality of performance requirements of a NoC, and generating a plurality of NoCs, each of the plurality of NoCs meeting a first subset of the plurality of performance requirements. For each of the plurality of NoCs, the example implementations involve presenting a difference between an actual performance of the each of the plurality of NoCs and each performance requirement of a second subset of the plurality of performance requirements and one or more costs for each of the plurality of NoCs.

Abstract: Example implementations as described herein are directed to systems and methods for processing a NoC specification for a plurality of performance requirements of a NoC, and generating a plurality of NoCs, each of the plurality of NoCs meeting a first subset of the plurality of performance requirements. For each of the plurality of NoCs, the example implementations involve presenting a difference between an actual performance of the each of the plurality of NoCs and each performance requirement of a second subset of the plurality of performance requirements and one or more costs for each of the plurality of NoCs.

Abstract: Example implementations as described herein are directed to systems and methods for processing a NoC specification for a plurality of performance requirements of a NoC, and generating a plurality of NoCs, each of the plurality of NoCs meeting a first subset of the plurality of performance requirements. For each of the plurality of NoCs, the example implementations involve presenting a difference between an actual performance of the each of the plurality of NoCs and each performance requirement of a second subset of the plurality of performance requirements and one or more costs for each of the plurality of NoCs.

Abstract: Systems and methods involving construction of a system interconnect in which different channels have different widths in numbers of bits. Example processes to construct such a heterogeneous channel NoC interconnect are disclosed herein, wherein the channel width may be determined based upon the provided specification of bandwidth and latency between various components of the system.

Abstract: In an aspect, the present disclosure provides a method that comprises automatic generation of a NoC from specified topological information based on projecting NoC elements of the NoC onto a grid layout. In an aspect, the specified topological information, including specification of putting constraints on positions/locations of NoC elements and links thereof, can be input by a user in real space, and can then be projected on the grid layout.