Abstract: Aspects of the disclosure relate to providing a secure collaboration between one or more PCIe accelerators and an enclave. An example system may include a PCIe accelerator apparatus. The PCIs accelerator apparatus may include the one or more PCIe accelerators and a microcontroller configured to provide a cryptographic identity to the PCIe accelerator apparatus. The PCIe accelerator apparatus may be configured to use the cryptographic identity to establish communication between the PCIe accelerator apparatus the enclave.

Abstract: Aspects of the disclosure relate to providing a secure collaboration between one or more PCIe accelerators and an enclave. An example system may include a PCIe accelerator apparatus. The PCIs accelerator apparatus may include the one or more PCIe accelerators and a microcontroller configured to provide a cryptographic identity to the PCIe accelerator apparatus. The PCIe accelerator apparatus may be configured to use the cryptographic identity to establish communication between the PCIe accelerator apparatus the enclave.

Abstract: Hardware transactions or other techniques, such as custom PCIe handling devices, are used to atomically move pages from one host's memory to another host's memory. The hosts are connected by one or two non-transparent bridges (NTBs), which make each host's memory and devices available to the other, while allowing each host to reboot independently.

Abstract: Aspects of the disclosure relate to providing a secure collaboration between one or more PCIe accelerators and an enclave. An example system may include a PCIe accelerator apparatus. The PCIs accelerator apparatus may include the one or more PCIe accelerators and a microcontroller configured to provide a cryptographic identity to the PCIe accelerator apparatus. The PCIe accelerator apparatus may be configured to use the cryptographic identity to establish communication between the PCIe accelerator apparatus the enclave.

Abstract: Hardware transactions or other techniques, such as custom PCIe handling devices, are used to atomically move pages from one host's memory to another host's memory. The hosts are connected by one or two non-transparent bridges (NTBs), which make each host's memory and devices available to the other, while allowing each host to reboot independently.

Abstract: Hardware transactions or other techniques, such as custom PCIe handling devices, are used to atomically move pages from one hoses memory to another hoses memory. The hosts are connected by one or two non-transparent bridges (NTBs), which make each host's memory and devices available to the other, while allowing each host to reboot independently.

Abstract: Hardware transactions or other techniques, such as custom PCIe handling devices, are used to atomically move pages from one hoses memory to another hoses memory. The hosts are connected by one or two non-transparent bridges (NTBs), which make each host's memory and devices available to the other, while allowing each host to reboot independently.

Abstract: Hardware transactions or other techniques, such as custom PCIe handling devices, are used to atomically move pages from one host's memory to another host's memory. The hosts are connected by one or two non-transparent bridges (NTBs), which make each host's memory and devices available to the other, while allowing each host to reboot independently.

Abstract: Aspects of the disclosure relate to directing and tracking translation lookaside buffer (TLB) shootdowns within hardware. One or more processors, comprising one or more processor cores, may determine that a process executing on a processing core causes one or more virtual memory pages to become disassociated with one or more previously associated physical memory addresses. The processing core which is executing that process which caused the disassociation may generate a TLB shootdown request. The processing core may transmit the TLB shootdown request to the other cores. The TLB shootdown request may include identification information, a shootdown address indicating the disassociated virtual memory page or pages which need to be flushed from the respective TLBs of the other cores, and a notification address indicating where the other cores may acknowledge completion of the TLB shootdown request.

Abstract: Aspects of the disclosure relate to providing a secure collaboration between one or more PCIe accelerators and an enclave. An example system may include a PCIe accelerator apparatus. The PCIs accelerator apparatus may include the one or more PCIe accelerators and a microcontroller configured to provide a cryptographic identity to the PCIe accelerator apparatus. The PCIe accelerator apparatus may be configured to use the cryptographic identity to establish communication between the PCIe accelerator apparatus the enclave.

Abstract: Hardware transactions or other techniques, such as custom PCIe handling devices, are used to atomically move pages from one host's memory to another host's memory. The hosts are connected by one or two non-transparent bridges (NTBs), which make each host's memory and devices available to the other, while allowing each host to reboot independently.

Abstract: Aspects of the disclosure relate to directing and tracking translation lookaside buffer (TLB) shootdowns within hardware. One or more processors, comprising one or more processor cores, may determine that a process executing on a processing core causes one or more virtual memory pages to become disassociated with one or more previously associated physical memory addresses. The processing core which is executing that process which caused the disassociation may generate a TLB shootdown request. The processing core may transmit the TLB shootdown request to the other cores. The TLB shootdown request may include identification information, a shootdown address indicating the disassociated virtual memory page or pages which need to be flushed from the respective TLBs of the other cores, and a notification address indicating where the other cores may acknowledge completion of the TLB shootdown request.

Abstract: Aspects of the disclosure relate to directing and tracking translation lookaside buffer (TLB) shootdowns within hardware. One or more processors, comprising one or more processor cores, may determine that a process executing on a processing core causes one or more virtual memory pages to become disassociated with one or more previously associated physical memory addresses. The processing core which is executing that process which caused the disassociation may generate a TLB shootdown request. The processing core may transmit the TLB shootdown request to the other cores. The TLB shootdown request may include identification information, a shootdown address indicating the disassociated virtual memory page or pages which need to be flushed from the respective TLBs of the other cores, and a notification address indicating where the other cores may acknowledge completion of the TLB shootdown request.

Abstract: Aspects of the disclosure relate to directing and tracking translation lookaside buffer (TLB) shootdowns within hardware. One or more processors, comprising one or more processor cores, may determine that a process executing on a processing core causes one or more virtual memory pages to become disassociated with one or more previously associated physical memory addresses. The processing core which is executing that process which caused the disassociation may generate a TLB shootdown request. The processing core may transmit the TLB shootdown request to the other cores. The TLB shootdown request may include identification information, a shootdown address indicating the disassociated virtual memory page or pages which need to be flushed from the respective TLBs of the other cores, and a notification address indicating where the other cores may acknowledge completion of the TLB shootdown request.