Abstract: A method includes defining a hierarchy associated with a test system including a plurality of test units for testing integrated circuit devices. At least some of the test units have a plurality of sockets. The hierarchy includes a first level including a first plurality of entities each associated with one of the sockets and at least a second level including a second plurality of entities each associated with a grouping of the sockets. State data associated with operational states of the sockets is received. A set of state metrics is generated for each entity at each level of the hierarchy based on the state data. Each set of state metrics identifies time spent in the operational states.

Abstract: A method includes defining a hierarchy associated with a test system including a plurality of test units for testing integrated circuit devices. At least some of the test units have a plurality of sockets. The hierarchy includes a first level including a first plurality of entities each associated with one of the sockets and at least a second level including a second plurality of entities each associated with a grouping of the sockets. State data associated with operational states of the sockets is received. A set of state metrics is generated for each entity at each level of the hierarchy based on the state data. Each set of state metrics identifies time spent in the operational states.

Abstract: A method includes retrieving a group test parameter determined based on test results associated with a plurality of integrated circuit devices. A particular integrated circuit device is tested using a test program and the group test parameter.

Abstract: A method includes retrieving a group test parameter determined based on test results associated with a plurality of integrated circuit devices. A particular integrated circuit device is tested using a test program and the group test parameter.

Abstract: A method and apparatus are provided for determining the health of a desired node in a multi-level system. The method includes defining a first fault model associated with a first node of a first level of the system, defining a second fault model associated with a second node of a second level of the system, and defining a third fault model associated with a third node associated with a third level of the system. The method further includes determining a health value associated with at least one of the first node, the second node, and the third node of the system based on at least one of the first fault model, second fault model, and the third fault model.

Abstract: A method for identifying a state of a manufacturing system includes defining at least one virtual sensor having a value. At least one state descriptor including a plurality of condition terms and a trigger probability is defined. Each condition term includes a function of the value of the virtual sensor. The condition terms are evaluated based on the value to determine a classification probability. The state is identified responsive to the classification probability being greater to or equal to the trigger probability. A manufacturing system including a plurality of tools, at least one virtual sensor, and a state classification unit is also provided.

Abstract: The present invention is generally directed to various methods of controlling gate electrode doping, and various systems for accomplishing same. In one illustrative embodiment, the method disclosed herein comprises performing at least one process operation to form a doped layer of gate electrode material, measuring a sheet resistance of the doped layer of gate electrode material and adjusting at least one parameter of at least one process if the measured sheet resistance does not fall within acceptable limits. In one embodiment, the system is comprised of a process tool for performing at least one process operation to form a doped layer of gate electrode material, a metrology tool for measuring a sheet resistance of the doped layer of gate electrode material and a controller for adjusting at least one parameter of at least one process operation if the measured sheet resistance of the doped layer of gate electrode material does not fall within acceptable limits.

Abstract: A method and apparatus is provided for fault detection spanning multiple processes. The method comprises receiving operational data associated with a first process, receiving operational data associated with a second process, which is downstream to the first process and performing fault detection analysis based on the operational data associated with the first process and second process using a common fault detection unit.

Abstract: The present invention is generally directed to an advanced process control of the manufacture of memory devices, and a system for accomplishing same. In one illustrative embodiment, the method comprises performing at least one process operation to form at least one layer of an oxide-nitride-oxide stack of a memory cell, the stack being comprised of a first layer of oxide positioned above a first layer of polysilicon, a layer of silicon nitride positioned above the first layer of oxide, and a second layer of oxide positioned above the layer of silicon nitride. The method further comprises measuring at least one characteristic of at least one of the first layer of polysilicon, the first oxide layer, the layer of silicon nitride, and the second layer of oxide and adjusting at least one parameter of at least one process operation used to form at least one of the first oxide layer, the layer of silicon nitride and the second oxide layer if the measured at least one characteristic is not within acceptable limits.

Abstract: A method and apparatus are provided for determining a next tool state based on fault detection information. The method comprises receiving operational data associated with processing of a workpiece by a processing tool, determining at least a portion of noise associated with the processing of the workpiece based on analyzing the operational data and estimating a next state of the processing tool based on at least the determined portion of the noise.

Abstract: A method and an apparatus for adjusting a process controller based upon a fault detection analysis. A process step upon a workpiece is performed using a processing tool. Manufacturing data relating to processing of the workpiece is acquired. The manufacturing data may include metrology data relating to the processed workpiece and/or tool state data relating to the tool state of a processing tool. A metrology/tool state data integration process is performed based upon the acquired manufacturing data. The metrology/tool state data integration process includes performing an assessment of a tool health related to the processing tool and adjusting an emphasis of the metrology data based upon the assessment of the tool health.

Abstract: A method and an apparatus for performing process control at an interconnect level. A process step upon a workpiece is performed. Manufacturing data relating to an interconnect location on the workpiece is acquired. An interconnect characteristic control process is performed based upon the manufacturing data. The interconnect characteristic control process includes controlling a process relating to a structure associated with the interconnect location on the workpiece to control a characteristic relating to the interconnect location.

Abstract: A method is provided for a process control based on tool health data. The method comprises processing a workpiece using a processing tool, receiving trace data associated with the processing of the workpiece from the processing tool and determining at least one value associated with a health of a portion of the processing tool based on at least a portion of the received trace data. The method further comprises adjusting processing of another workpiece based on the determined health value.

Abstract: A method and an apparatus for the determination of a process flow based upon fault detection. A process step upon a workpiece is performed. Fault detection analysis based upon the process step performed upon the workpiece is performed. A workpiece routing process is performed based upon the fault detection analysis. The wafer routing process includes using a controller to perform one or a rework process routing, a non-standard process routing, a fault verification process routing, a normal process routing, or a termination process routing, based upon the fault detection analysis.

Abstract: A method and an apparatus for performing process control at an interconnect level. A process step upon a workpiece is performed. Manufacturing data relating to an interconnect location on the workpiece is acquired. An interconnect characteristic control process is performed based upon the manufacturing data. The interconnect characteristic control process includes controlling a process relating to a structure associated with the interconnect location on the workpiece to control a characteristic relating to the interconnect location.