Abstract: A method and system for reducing glitch effects in combinational logic is presented. If combinational logic incurs a particle-induced single event transient (SET) signal, a glitch reducing circuit, which is connected in a signal path between the combinational logic and downstream logic, will prevent the SET from propagating to the downstream logic. The glitch reducing circuit functions as a signal filter that provides a SET-filtered drive signal to downstream logic. The glitch reducing circuit receives both the input to the combinational logic and the output from the combinational logic. The input acts to enable or disable the glitch reducing circuit, so that for certain input values, the glitch reducing circuit passes the logic output signal to downstream logic, and for other input values, the glitch reducing circuit blocks the output signal from passing to downstream logic.