Abstract: A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design for image processing, and more specifically to vector units for supporting image processing is provided. A combined vector/scalar unit is provided wherein one or more processing lanes of the vector unit are used for performing scalar operations. An integrated register file is also provided for storing vector and scalar data. Therefore, the transfer of data to memory to exchange data between independent vector and scalar units is obviated and a significant amount of chip area is saved.

Abstract: A cup holder is mountable onto the top of an extendable handle projecting from the top of a piece of wheeled luggage. The cup holder holds a cup of liquid while the luggage is being pulled around. The cup holder is constructed from a stretchy fabric with a handle sleeve that resiliently grips the top of the extended luggage handle. The flexibility of the fabric material provides the cup support, in the form of a truncated hollow cone, with a way of rotating freely with respect to the luggage handle so that a self-leveling action is provided without need of a mechanical hinge.

Abstract: According to embodiments of the invention, a data structure may be created which may be used by both a ray tracing unit and by a rendering engine. The data structure may have an initial or upper portion representing bounding volumes which partition a three-dimensional scene and a second or lower portion representing objects within the three-dimensional scene. The integrated acceleration data structure may be used by a rendering engine to render a two-dimensional image from a three-dimensional scene, and by a ray tracing unit to perform intersection tests.

Abstract: A method, computer-readable medium, and an apparatus for generating a transcendental value. The method includes receiving an input containing an input value and an opcode and determining whether the opcode corresponds to a trigonometric operation or a power-of-two operation. The method also includes calculating a fractional value and an integer value from the input value, generating the transcendental value based on the fractional value by adding at least a portion of the fractional value with at least one of a shifted fractional value produced by shifting the portion of the fractional value and a constant value, and providing the transcendental value in response to the request. In this fashion, the same circuit area may be used to carry out both trigonometric and power-of-two calculations, leading to greater circuit area savings and performance advantages while not sacrificing significant accuracy.

Abstract: Embodiments of the invention are generally related to the field of image processing, and more specifically to vector units for supporting image processing. A vector unit may comprise a plurality of operand multiplexers associated with each vector processing lane of the vector unit. The operand multiplexers may select vector operands from one or more register files for performing a cross product operation. A first multiply operation may be performed in a first pipeline stage by multiplying a first set of operands in a multiplier. In a second pipeline stage, a second multiply operation may be performed by multiplying a second set of operands. The results of the first multiply operation and the second multiply operation may be transferred to an adder to complete the cross product instruction.

Abstract: Embodiments of the invention provide logic within the store data path between a processor and a memory array. The logic may be configured to misalign vector data as it is stored to memory. By misaligning vector data as it is stored to memory, memory bandwidth may be maximized while processing bandwidth required to store vector data misaligned is minimized. Furthermore, embodiments of the invention provide logic within the load data path which allows vector data which is stored misaligned to be aligned as it is loaded into a vector register. By aligning misaligned vector data as it is loaded into a vector register, memory bandwidth may be maximized while processing bandwidth required to align misaligned vector data may be minimized.

Abstract: According to one embodiment of the invention, by increasing the number of rays issued through adjacent pixels with colors of high contrast while maintaining the number of rays issued through adjacent pixels which do not have colors of high contrast, a ray tracing image processing system may render an anti-aliased image while minimizing the increase in workload experienced by the image processing system. Additionally, according to another embodiment of the invention, by maintaining the number of rays issued through adjacent pixels which have colors of low contrast while increasing the number of rays issued through adjacent pixels which do not have colors of low contrast, the image processing system may reduce workload experienced while performing ray tracing while maintaining the quality of the rendered image.

Abstract: According to embodiments of the invention, a step value and a step-interval cache coherency protocol may be used to update and invalidate data stored within cache memory. A step value may be an integer value and may be stored within a cache directory entry associated with data in the memory cache. Upon reception of a cache read request, along with the normal address comparison to determine if the data is located within the cache a current step value may be compared with the stored step value to determine if the data is current. If the step values match, the data may be current and a cache hit may occur. However, if the step values do not match, the requested data may be provided from another source. Furthermore, an application may update the current step value to invalidate old data stored within the cache and associated with a different step value.

Abstract: Embodiments of the invention provide logic within the store data path between a processor and a memory array. The logic may be configured to misalign vector data as it is stored to memory. By misaligning vector data as it is stored to memory, memory bandwidth may be maximized while processing bandwidth required to store vector data misaligned is minimized. Furthermore, embodiments of the invention provide logic within the load data path which allows vector data which is stored misaligned to be aligned as it is loaded into a vector register. By aligning misaligned vector data as it is loaded into a vector register, memory bandwidth may be maximized while processing bandwidth required to align misaligned vector data may be minimized.

Abstract: A method for bridging between a high speed computer processor bus and a high speed output bus. The preferred embodiment is a method for bridging between a GPUL bus for a GPUL PowerPC microprocessor from International Business Machines Corporation (IBM) and an output high speed interface (MPI).

Abstract: A bus bridge between a high speed computer processor bus and a high speed output bus. The preferred embodiment is a bus bridge between a GPUL bus for a GPUL PowerPC microprocessor from International Business Machines Corporation (IBM) and an output high speed interface (MPI). Another preferred embodiment is a bus bridge in a bus transceiver on a multi-chip module.

Abstract: A method, computer-readable medium, and apparatus for context switching between a first thread and a second thread. The method includes detecting an exception, wherein the exception is generated in response to receiving a packet of information directed to one of the first thread and the second thread, and in response to detecting the exception, invoking an exception handler. The exception handler is configured to execute one or more instructions removing access to at least a portion of a processor cache. The portion of the processor cache contains cached information for the first thread using a first address translation. Removing access to the portion of the processor cache prevents the second thread using a second address translation from accessing the cached information in the processor cache. The exception handler is also configured to branch to at least one of the first thread and the second thread.

Abstract: According to one embodiment of the invention, by increasing the number of rays issued through adjacent pixels with colors of high contrast while maintaining the number of rays issued through adjacent pixels which do not have colors of high contrast, a ray tracing image processing system may render an anti-aliased image while minimizing the increase in workload experienced by the image processing system. Additionally, according to another embodiment of the invention, by maintaining the number of rays issued through adjacent pixels which have colors of low contrast while increasing the number of rays issued through adjacent pixels which do not have colors of low contrast, the image processing system may reduce workload experienced while performing ray tracing while maintaining the quality of the rendered image.

Abstract: An accessory communicates with a portable media device (“PMD”) to store tags associated with broadcasts in a file maintained in a storage medium of the accessory, where the tags contain information descriptive of a subset of the broadcast content. In one embodiment, the accessory sends commands to the PMD to create or open a tag file that resides on the PMD, write one or more tags to the file, and close the file. Stored tags can be used to access (e.g., purchase) tagged content by communicating with a media asset delivery service either via a host computer or directly from the PMD.

Abstract: According to embodiments of the invention, rays may be stochastically culled before they are issued into the three-dimensional scene. Stochastically culling rays may reduce the number of rays which need to be traced by the image processing system. Furthermore, by stochastically culling rays before they are issued into the three-dimensional scene, minor imperfections may be added to the final rendered image, thereby improving the realism of the rendered image. Therefore, stochastic culling of rays may improve the performance of the image processing system by reducing workload imposed on the image processing system and improving the realism of the images rendered by the image processing system. According to another embodiment of the invention, the realism of images rendered by the image processing system may also be improved by stochastically adding secondary rays after ray-primitive intersections have occurred.

Abstract: According to embodiments of the invention, rays may be stochastically culled before they are issued into the three-dimensional scene. Stochastically culling rays may reduce the number of rays which need to be traced by the image processing system. Furthermore, by stochastically culling rays before they are issued into the three-dimensional scene, minor imperfections may be added to the final rendered image, thereby improving the realism of the rendered image. Therefore, stochastic culling of rays may improve the performance of the image processing system by reducing workload imposed on the image processing system and improving the realism of the images rendered by the image processing system. According to another embodiment of the invention, the realism of images rendered by the image processing system may also be improved by stochastically adding secondary rays after ray-primitive intersections have occurred.

Abstract: The present invention is generally related to the field of image processing, and more specifically to an instruction set for processing images. Vector processing may involve rearranging vector operands in one or more source registers prior to performing vector operations. Typically, rearranging of operands in source registers is done by issuing a plurality of permute instructions that require excessive usage of temporary registers. Furthermore, the permute instructions may cause dependencies between instructions executing in a pipeline, thereby adversely affecting performance. Embodiments of the invention provide a level of muxing between a register file and a vector unit that allow for rearrangement of vector operands in source registers prior to providing the operands to the vector unit, thereby obviating the need for permute instructions.

Abstract: According to embodiments of the invention, secondary rays may be pooled after they are generated by a vector throughput engine. After pooling the secondary rays, they may be reordered according to similarities in trajectory and originating location. The secondary rays may be sent in the new order to a workload manager for spatial index traversal. The reordering of the secondary rays may cause rays which traverse similar portions of the spatial index to be traversed immediately following (or shortly thereafter) one another. Consequently, the necessary portions of the spatial index may remain within the workload manager's memory cache, thereby reducing the number of cache misses and the amount of time necessary to traverse secondary rays through the spatial index. The reduction in time necessary to traverse the secondary rays through the spatial index may improve the overall performance of the image processing system.

Abstract: By mapping leaf nodes of a spatial index to processing elements, efficient distribution of workload in an image processing system may be achieved. In addition, processing elements may use a thread table to redistribute workload from processing elements which are experiencing an increased workload to processing elements which may be idle. Furthermore, the workload experienced by processing elements may be monitored in order to determine if workload is balanced. Periodically the leaf nodes for which processing elements are responsible may be remapped in response to a detected imbalance in workload. By monitoring the workload experienced by the processing elements and remapping leaf nodes to different processing elements in response to unbalanced workload, efficient distribution of workload may be maintained. Efficient distribution of workload may improve the performance of the image processing system.

Abstract: Embodiments of the invention provide methods and systems to reduce the amount of space necessary to store a spatial index. According to embodiments of the invention, a spatial index may store pointers to information defining primitives which are located within bounding volumes defined by leaf nodes in the spatial index. The pointers may be smaller in size in contrast to information which defines the primitives, and the pointers may point to locations within a scene graph which contains information defining the primitives. Therefore, by storing pointers to primitives in the spatial index rather than the information which defines the primitives, the amount of space required to store the spatial index may be reduced.