Abstract: An arrangement is provided for selectively accessing and testing a digital telecommunications circuit (1) without detriment to the integrity of a signal carried thereby. The arrangement comprises an access unit (10) inserted in the circuit (1) to be tested, and test equipment (11) connected to the access unit (10) and through which the circuit to be tested can be selectively routed. The test equipment (11) includes a shift register (24) in its test circuit path. In order to match the delay introduced by the shift register (24) in the test circuit path, a similar clocked delay (21) is included in the access unit in the route followed by the telecommunications circuit (1) when undiverted. This delay matching avoids signal loss or repetition when switching the circuit to be tested between its undiverted and diverted paths.