Patents by Inventor Eric Palmer

Eric Palmer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250056398
    Abstract: Various arrangements for facilitating multi-network systems are provided. A private access point controller may be connected to a general network. The private access point controller may be configured to determine that a wireless device is connected to the general network, and in response to determining that the wireless device is connected to the general network, transmit, to the wireless device via the general network, first credentials configured to enable the wireless device to access a first private network.
    Type: Application
    Filed: October 29, 2024
    Publication date: February 13, 2025
    Inventors: Aram Semerjyan, Eric Palmer
  • Publication number: 20250005720
    Abstract: The lack of knowledge about a downstream consumer using a resized image can lead to poor inference quality of a machine learning model. Inference quality can be improved when the resizing algorithm to produce resized images closely matches the one used during training of the machine learning model. To achieve this technical task, a resizer can be made aware of downstream consumer information and apply a suitable resizing algorithm. In one scenario, the downstream consumer information is received as metadata from a downstream process. In another scenario, an optimal resizing option can be determined to maximize inference quality. In yet another scenario, a likely resizing option can be determined by assessing a filtering profile determined based on a known original image and a known resized image.
    Type: Application
    Filed: September 11, 2024
    Publication date: January 2, 2025
    Applicant: Intel Corporation
    Inventors: Sebastian Possos, Penne Lee, Yi-jen Chiu, Eric Palmer
  • Patent number: 12143929
    Abstract: Various arrangements for facilitating digital content in multi-network television receiver communication systems are provided. A general network access point can provide access to a general network. A private network access point can provide access to a private network. Credentials for accessing the private network are distributed by a primary television receiver configured to determine that a secondary television receiver is connected to the general network via the general network access point. In response, the primary television receiver transmits, via the general network, credentials configured to enable the secondary television receiver to access the private network via the private network access point to the secondary television receiver. The primary television receiver is further configured to transmit, via the private network, digital media content to the secondary television receiver.
    Type: Grant
    Filed: May 26, 2022
    Date of Patent: November 12, 2024
    Assignee: DISH Network L.L.C.
    Inventors: Aram Semerjyan, Eric Palmer
  • Publication number: 20230388913
    Abstract: Various arrangements for facilitating digital content in multi-network television receiver communication systems are provided. A general network access point can provide access to a general network. A private network access point can provide access to a private network. Credentials for accessing the private network are distributed by a primary television receiver configured to determine that a secondary television receiver is connected to the general network via the general network access point. In response, the primary television receiver transmits, via the general network, credentials configured to enable the secondary television receiver to access the private network via the private network access point to the secondary television receiver. The primary television receiver is further configured to transmit, via the private network, digital media content to the secondary television receiver.
    Type: Application
    Filed: May 26, 2022
    Publication date: November 30, 2023
    Inventors: Aram Semerjyan, Eric Palmer
  • Patent number: 9665097
    Abstract: A flight control system for an aircraft includes at least one flight control computer that carries out a ground lift dump function that selectively extends a spoiler located on a wing of the aircraft into an airflow passing over the wing. The at least one flight control computer includes arming logic that is responsive to an input signal indicative of an aircraft parameter to automatically arm the ground lift dump function during certain phases of operation of the aircraft. The at least one flight control computer includes spoiler deployment logic that is responsive to an arming signal from the aiming logic which indicates that the ground lift function is armed to deploy the spoiler into its extended position within the airflow passing over the wing of the aircraft to assist in stopping the aircraft while the aircraft is on the ground.
    Type: Grant
    Filed: June 11, 2014
    Date of Patent: May 30, 2017
    Assignee: BOMBARDIER INC.
    Inventors: Antoine Letang, Florian Chedaleux, Vincent Poudou, Lawrence Oberfeld, Eric Palmer
  • Publication number: 20160139597
    Abstract: A flight control system for an aircraft includes at least one flight control computer that carries out a ground lift dump function that selectively extends a spoiler located on a wing of the aircraft into an airflow passing over the wing. The at least one flight control computer includes arming logic that is responsive to an input signal indicative of an aircraft parameter to automatically arm the ground lift dump function during certain phases of operation of the aircraft. The at least one flight control computer includes spoiler deployment logic that is responsive to an arming signal from the aiming logic which indicates that the ground lift function is armed to deploy the spoiler into its extended position within the airflow passing over the wing of the aircraft to assist in stopping the aircraft while the aircraft is on the ground.
    Type: Application
    Filed: June 11, 2014
    Publication date: May 19, 2016
    Inventors: Antoine LETANG, Florian CHEDALEUX, Vincent POUDOU, Lawrence OBERFELD, Eric PALMER
  • Patent number: 8188594
    Abstract: A high-speed I/O trace is part of an I/O package architecture for an integrated circuit package substrate. The integrated circuit package substrate includes an integrated heat spreader footprint on a die-side and the I/O trace to couple with an IC device to be disposed inside the IHS footprint. The I/O trace includes a pin-out terminal outside the IHS footprint to couple to an IC device to be disposed outside the IHS footprint. The high-speed I/O trace can sustain a data flow rate from a processor in a range from 5 gigabits per second (Gb/s) to 40 Gb/s.
    Type: Grant
    Filed: October 1, 2009
    Date of Patent: May 29, 2012
    Assignee: Intel Corporation
    Inventors: Sanka Ganesan, Kemal Aygun, Chandrashekhar Ramaswamy, Eric Palmer, Henning Braunisch
  • Patent number: 7705447
    Abstract: A high-speed I/O trace is part of an I/O package architecture for an integrated circuit package substrate. The integrated circuit package substrate includes an integrated heat spreader footprint on a die-side and the I/O trace to couple with an IC device to be disposed inside the IHS footprint. The I/O trace includes a pin-out terminal outside the IHS footprint to couple to an IC device to be disposed outside the IHS footprint. The high-speed I/O trace can sustain a data flow rate from a processor in a range from 5 gigabits per second (Gb/s) to 40 Gb/s.
    Type: Grant
    Filed: September 29, 2008
    Date of Patent: April 27, 2010
    Assignee: Intel Corporation
    Inventors: Sanka Ganesan, Kemal Aygun, Chandrashekhar Ramaswamy, Eric Palmer, Henning Braunisch
  • Publication number: 20100096743
    Abstract: A high-speed I/O trace is part of an I/O package architecture for an integrated circuit package substrate. The integrated circuit package substrate includes an integrated heat spreader footprint on a die-side and the I/O trace to couple with an IC device to be disposed inside the IHS footprint. The I/O trace includes a pin-out terminal outside the IHS footprint to couple to an IC device to be disposed outside the IHS footprint. The high-speed I/O trace can sustain a data flow rate from a processor in a range from 5 gigabits per second (Gb/s) to 40 Gb/s.
    Type: Application
    Filed: October 1, 2009
    Publication date: April 22, 2010
    Inventors: Sanka Ganesan, Kemal Aygun, Chandrashekhar Ramaswamy, Eric Palmer, Henning Braunisch
  • Publication number: 20100078781
    Abstract: A high-speed I/O trace is part of an I/O package architecture for an integrated circuit package substrate. The integrated circuit package substrate includes an integrated heat spreader footprint on a die-side and the I/O trace to couple with an IC device to be disposed inside the IHS footprint. The I/O trace includes a pin-out terminal outside the IHS footprint to couple to an IC device to be disposed outside the IHS footprint. The high-speed I/O trace can sustain a data flow rate from a processor in a range from 5 gigabits per second (Gb/s) to 40 Gb/s.
    Type: Application
    Filed: September 29, 2008
    Publication date: April 1, 2010
    Inventors: Sanka Ganesan, Kemal Aygun, Chandrashekhar Ramaswamy, Eric Palmer, Henning Braunisch
  • Publication number: 20070117339
    Abstract: A method for forming an plurality of paths on a substrate includes drilling an opening for a via to a depth to expose a first pad and a second pad, lining the opening with a conductive material, and insulating a first portion of the lining in the opening from a second portion of the lining in the opening to form a first electrical path contacting the first pad and a second electrical path contacting the second pad.
    Type: Application
    Filed: January 24, 2007
    Publication date: May 24, 2007
    Inventors: Todd Myers, Nicholas Watts, Eric Palmer, Renee Defeo, Jui Lim
  • Publication number: 20050224989
    Abstract: A method of forming a device associated with a via includes forming an opening or via, and forming at least a pair of conducting paths within the via. Also disclosed is a via having at pair of conducting paths therein.
    Type: Application
    Filed: March 31, 2004
    Publication date: October 13, 2005
    Inventors: Todd Myers, Nicholas Watts, Eric Palmer, Jui Lim
  • Publication number: 20050133918
    Abstract: A system includes a device having at least one integrated circuit. The integrated circuit further includes a first layer of conductive material, a second layer of conductive material, and a via having multiple electrical paths for interconnecting the first layer of conductive material and the second layer of conductive material. A method for forming a via includes drilling an opening to a depth to expose a first pad and a second pad, lining the opening with a conductive material, and insulating a first portion of the lining in the opening from a second portion of the lining in the opening to form a first electrical path contacting the first pad and a second electrical path contacting the second pad.
    Type: Application
    Filed: December 17, 2003
    Publication date: June 23, 2005
    Inventors: Todd Myers, Nicholas Watts, Eric Palmer, Renee Defeo, Jui Lim
  • Publication number: 20050121769
    Abstract: In some embodiments, a method includes providing a substrate, providing a coverlay blank, laminating the coverlay blank to the substrate, and forming at least one opening in the coverlay blank by photolithography.
    Type: Application
    Filed: December 5, 2003
    Publication date: June 9, 2005
    Inventors: Nicholas Watts, Eric Palmer, Jui Lim, Todd Myers, Boonsri Wangmaneerat
  • Patent number: 6362823
    Abstract: A method for utilizing an intellectual structure for visualizing a system of multi-variate data points in a parallel coordinate system, identifying an area of interest within the system, and then transforming a selected portion of the system for visualization in single-point representations of n-dimensional points using broken-line parallel coordinates, where the n point representations of conventional parallel coordinates are brought back into a single point representation that is the single point vector resultant of n dimensional spaces viewable in familiar three dimensional display space.
    Type: Grant
    Filed: June 25, 1999
    Date of Patent: March 26, 2002
    Assignee: N-Dimensional Visualization
    Inventors: Robert R. Johnson, Marc Palmer, Eric Palmer, Rodney D. Millar
  • Patent number: 4643324
    Abstract: The disclosure relates to a waste bin having an inner steel container for refuse and an outer thermoplastic hood form cover having a domed top wall and side ports through which refuse may be deposited in the container. A lid for the container is mounted on the underside of the top wall of the cover and is supported on a central stud extending through the cover by means of a polythene washer held on the stud by a nut. If a fire should develop in the container the resulting heat will cause the washer to melt releasing the cover to fall onto the top of the container therefore preventing air flow into the container to restrict and extinguish the fire.
    Type: Grant
    Filed: March 19, 1986
    Date of Patent: February 17, 1987
    Assignee: Glasdon Limited
    Inventor: Eric Palmer