Abstract: A method for automating semiconductor design using a graph neural network (GNN) and transformer architecture. The method includes receiving a netlist of an integrated circuit from an electronic design automation tool, identifying transistors as nodes, and creating a GNN that connects these nodes. The method generates node embeddings for the GNN, orders the node embeddings, and performs parasitic extraction between nodes to generate parasitic extraction values. The method then generates a placement order of the transistors for physical layout based on specified design parameter values of performance and power and other metrics.

Abstract: A method for automating semiconductor design involves receiving a netlist of an integrated circuit, generating a candidate layout using a permutation generator, and creating embeddings from the layout with a first machine learning model. The method includes generating parasitic extraction data values using a second machine learning model, comparing these values against predetermined design rule constraints to identify a design rule constraint score, and assigning a reward based on this score. The reward is transmitted to a reinforcement learning agent that modifies the permutation generator. The system outputs the candidate layout, parasitic extraction data, and design rule constraint score to a memory store.

Abstract: A method and system for parasitic extraction in semiconductor layouts using spatial localization and point reduction, thereby improving efficiency of predictive models for identifying parasitic capacitance in electronic circuit design. Candidate physical layouts are generated from electrical design. Transistors and wiring are spatially modeled as three-dimensional structures. Geometrical points are identified from the three-dimensional structures being modeled and used as nodes in a neural network. A subset of the nodes is selected, and the subset is further limited to a limited region surrounding the given node to be evaluated. Nodes can have weighting based on relative geometrical position. Parasitic extraction is performed on the limited number of nodes for efficient evaluation of candidate layouts.

Abstract: A method and system for parasitic extraction in semiconductor layouts using localized weighting and a federated learning model. The process involves receiving a layout design of an integrated circuit, generating nodes representing geometrical points, and assigning weights based on node location and material. A self-attention network identifies a subset of nodes for parasitic extraction, generating extraction data linked to physical design patterns. The method incorporates this data into a machine learning model for parasitic extraction, updating the machine learning model with layouts from various process design kits. The system aggregates and converts extraction data into a 2D format for graphical display, enhancing design analysis and prediction accuracy.

Abstract: A method for automating semiconductor design using a graph neural network (GNN) and a generative adversarial network (GAN) for layout generation. The method includes receiving a netlist of an integrated circuit from an electronic design automation tool, identifying transistors as nodes, and creating a GNN that connects these nodes. The method generates node embeddings for the GNN, orders the node embeddings, and performs parasitic extraction between nodes to generate parasitic extraction values. The GAN evaluates and modifies the order of node embeddings to optimize design parameters such as performance and power. The method then generates a physical layout design based on the optimized order of node embeddings and outputs the design to a memory store. The process can iterate to further refine the layout, ensuring it meets specified design criteria including area and cost.

Abstract: A method for automating semiconductor design is disclosed, which includes optimizing integrated circuit layouts using latent space models and reinforcement learning. The described method enables efficient physical layout design by generating embeddings from a process design kit, placing them in a latent space representation model and producing candidate physical layouts. Resistance-capacitance values are extracted, and reward values are assigned to guide the reinforcement learning model. This process iteratively refines the generative layout synthesis model, enhancing design rule checking scores and efficiency. Primary application is in electronic design automation (EDA) for integrated circuits, improving design accuracy and reducing processing time.

Abstract: Aspects of the present disclosure provide a die-to-die hybrid bonding method. The die-to-die hybrid bonding method includes obtaining a metal etch depth profile value for each die from a first group of dies and for each die from a second group of dies, the metal etch depth profile value of each die representing a copper (Cu) recess depth of a bonding region of the respective die; based on the metal etch depth profile values, executing a die pairing process that pairs each die from the first group of dies with a corresponding die from the second group of dies to form a plurality of pairs of dies, an aggregate metal etch depth profile value of each pair of dies being within a predetermined range; and bonding the plurality of pairs of dies through an anneal process.

Abstract: In an implementation, energy reaching the lower surface of a photoresist may be redirected back into the photoresist material. This may be done by, for example, reflecting and/or fluorescing the energy from a hardmask provided on the wafer surface back into the photoresist.

Abstract: According to an embodiment of the invention, an adjustable EUV light source may be used for photolithography. The EUV light source, such as an electrode, is mounted in an adjustable housing. The housing can be adjusted to change the distance between the light source and focusing mirrors, which in turn changes the partial coherence value of the system. The partial coherence value can be changed to print different types of semiconductor features.

Abstract: A detector for extreme ultraviolet (EUV) energy uses incidence reflectance of the EUV beam off the detector to both capture a small but controllable fraction of the EUV energy and to redirect most of the energy to its target. In one embodiment, a reflective coating of material on a sensor surface is used. In another embodiment, a multi-layer reflector on a sensor is used. A method of making the multi-layer reflector/sensor is also described.

Abstract: According to a first embodiment of the invention, a dual cathode electrode for generating EUV light is disclosed. The dual cathode electrode may include a first outer cathode, a second inner cathode, and an anode disposed between the inner and outer cathodes. The dual cathode electrode also includes a plasma disposed in between the cathodes that emits EUV photons when it is excited by an arc between the anode and the cathodes. According to a second embodiment of the invention, several Dense Plasma Focus (DPF) electrodes are placed along a circle. The DPF electrodes, when activated, will emit electron photons from the circle in which they are placed thereby avoiding obscuration used to protect UV mirrors against debris.

Abstract: In an implementation, energy reaching the lower surface of a photoresist may be redirected back into the photoresist material. This may be done by, for example, reflecting and/or fluorescing the energy from a hardmask provided on the wafer surface back into the photoresist.

Abstract: In an implementation, energy reaching the lower surface of a photoresist may be redirected back into the photoresist material. This may be done by, for example, reflecting and/or fluorescing the energy from a hardmask provided on the wafer surface back into the photoresist.

Abstract: According to a first embodiment of the invention, a dual cathode electrode for generating EUV light is disclosed. The dual cathode electrode may include a first outer cathode, a second inner cathode, and an anode disposed between the inner and outer cathodes. The dual cathode electrode also includes a plasma disposed in between the cathodes that emits EUV photons when it is excited by an arc between the anode and the cathodes. According to a second embodiment of the invention, several Dense Plasma Focus (DPF) electrodes are placed along a circle. The DPF electrodes, when activated, will emit electron photons from the circle in which they are placed thereby avoiding obscuration used to protect UV mirrors against debris.

Abstract: According to an embodiment of the invention, an adjustable EUV light source may be used for photolithography. The EUV light source, such as an electrode, is mounted in an adjustable housing. The housing can be adjusted to change the distance between the light source and focusing mirrors, which in turn changes the partial coherence value of the system. The partial coherence value can be changed to print different types of semiconductor features.

Abstract: In an implementation, energy reaching the lower surface of a photoresist may be redirected back into the photoresist material. This may be done by, for example, reflecting and/or fluorescing the energy from a hardmask provided on the wafer surface back into the photoresist.

Abstract: A detector for extreme ultraviolet (EUV) energy uses incidence reflectance of the EUV beam off the detector to both capture a small but controllable fraction of the EUV energy and to redirect most of the energy to its target. In one embodiment, a reflective coating of material on a sensor surface is used. In another embodiment, a multi-layer reflector on a sensor is used. A method of making the multi-layer reflector/sensor is also described.