Abstract: A first semiconductor build has a first back end of the line having a dielectric stack, metal wiring lines, vias and joining pads that are constructed into a first electrical connected path, having a first and second end, and passing through a portion of the first back end of the line dielectric stack. A second semiconductor build has a similar first electrical connected path. The first and second builds are bonded to a third semiconductor build, with the second end of the first electrical connected path of the first semiconductor build and the first end of the first electrical connected path of the second semiconductor build electrically coupled together in series via a first electrical connected path of the third semiconductor build, such that the resistance/conductivity measured from the first end of the first semiconductor build to the second end of the second semiconductor build verifies conductivity of the paths.

Abstract: A semiconductor structure includes a semiconductor wafer having an insulating surface and a plurality of metal pads thereon; and a plurality of individual semiconductor dies having a front side and a back side. Each die has an insulating surface and metal pads on the front side. The plurality of individual semiconductor dies are positioned over and hybrid bonded to the semiconductor wafer and respective metal pads and insulating surfaces of the semiconductor wafer and the plurality of semiconductor dies are aligned and hybrid bonded face to face. An encapsulating material is positioned over the semiconductor wafer and the plurality of semiconductor dies to provide mechanical stability and an insulating surface over the plurality of individual semiconductor dies.

Abstract: A semiconductor element includes a conductive pad. The semiconductor element further includes a first layer of a first polyimide material having an uppermost surface. The first layer includes a via trench extending through the first layer from the uppermost surface to the conductive pad. The semiconductor element further includes a second layer of a second polyimide material arranged in direct contact with the uppermost surface. The second layer includes a line trench extending to the uppermost surface. The semiconductor element further includes a conductive structure arranged in the via trench and the line trench such that copper is in direct contact with the second polyimide material.

Abstract: A first semiconductor build has a first back end of the line having a dielectric stack, metal wiring lines, vias and joining pads that are constructed into a first electrical connected path, having a first and second end, and passing through a portion of the first back end of the line dielectric stack. A second semiconductor build has a similar first electrical connected path. The first and second builds are bonded to a third semiconductor build, with the second end of the first electrical connected path of the first semiconductor build and the first end of the first electrical connected path of the second semiconductor build electrically coupled together in series via a first electrical connected path of the third semiconductor build, such that the resistance/conductivity measured from the first end of the first semiconductor build to the second end of the second semiconductor build verifies conductivity of the paths.

Abstract: A stack structure that includes: a device wafer, a handler wafer, and a bonding structure disposed between the device wafer and the handler wafer, wherein one or both of the device wafer and the handler wafer have a release layer that is configured to be substantially or completely vaporized by infrared ablation when exposed to an infrared laser energy. The device wafer includes at least two consecutive layers adjacent the bonding structure that together include a plurality of fill portions that substantially or completely disable entry of the infrared laser energy into a plurality of layers of the device wafer below the two consecutive layers adjacent the bonding structure.

Abstract: A three-dimensional (3D) die architecture is provided. The 3D die architecture includes a first die and a second die. The second die includes multiple interior layers of various types and is hybrid bonded to the first die along a hybrid bond layer. The 3D die architecture further includes oxide liner material extending from an exposed surface of the second die to the hybrid bond layer, a first through-silicon-via (TSV) extending from the exposed surface to a corresponding one of the multiple interior layers and a second TSV extending within the oxide liner material from the exposed surface to the hybrid bond layer.

Abstract: A stack structure that includes: a device wafer, a handler wafer, and a bonding structure disposed between the device wafer and the handler wafer, wherein one or both of the device wafer and the handler wafer have a release layer that is configured to be substantially or completely vaporized by infrared ablation when exposed to an infrared laser energy. The device wafer includes at least two consecutive layers adjacent the bonding structure that together include a plurality of fill portions that substantially or completely disable entry of the infrared laser energy into a plurality of layers of the device wafer below the two consecutive layers adjacent the bonding structure.

Abstract: A hybrid bonded semiconductor structure includes a first substrate and a second substrate each having an interface joined in a hybrid bond. Each substrate has a die portion and a crackstop structure adjacent the die portion. One or more voids in the first substrate and the second substrate are formed in or about a portion of a periphery of each crackstop structure. At least some of the one or more voids in the first substrate and the second substrate are substantially aligned to form a unified void with airgaps across the hybrid bond interface.

Abstract: A semiconductor element includes a conductive pad. The semiconductor element further includes a first layer of a first polyimide material having an uppermost surface. The first layer includes a via trench extending through the first layer from the uppermost surface to the conductive pad. The semiconductor element further includes a second layer of a second polyimide material arranged in direct contact with the uppermost surface. The second layer includes a line trench extending to the uppermost surface. The semiconductor element further includes a conductive structure arranged in the via trench and the line trench such that copper is in direct contact with the second polyimide material.

Abstract: A multi-chip semiconductor device with multi-level structure including a substrate with a top substrate surface, a cavity with a depth in the substrate, a first chip having a top first chip surface with a first chip height, optionally including a second chip having a top second chip surface with a second chip height, and a connecting passive chip bridging the first chip, the second chip and the substrate by solder bumps wherein the solder bumps enable the connecting passive chip to be level.

Abstract: A method for constructing a composite solder transfer moldplate for flip chip wafer bumping of a substrate, comprising the steps of coating at least one polymer layer onto a first side of a transparent plate, the plate having a thermal expansion coefficient similar to that of the substrate; and forming a multiplicity of cavities in a polymer layer on one side of the plate, each cavity being for receiving solder. A moldplate made by the method. The structure has required behavior through temperature excursions between room temperature and various solder molten temperatures.

Abstract: Sealing a via using a soventless, low viscosity, high temperature stable polymer or a high solids content polymer solution of low viscosity, where the polymeric material is impregnated within the via at an elevated temperature. A supply chamber is introduced to administer the polymeric material at an elevated temperature, typically at a temperature high enough to liquefy the polymeric material. The polymeric material is introduced through heated supply lines under force from a pump, piston, or a vacuum held within said supply chamber.