Abstract: A half-bridge switch arrangement has a plurality of parallel-connected half-bridges, each half-bridge having a first semiconductor switching element and a second semiconductor switching element, has a first busbar, to which a first terminal of each of the first semiconductor switching elements is electrically connected, a second busbar, to which a second terminal of each of the first semiconductor switching elements and a first terminal of each of the second semiconductor switching elements are electrically connected, and has a third busbar, to which a second terminal of each of the second semiconductor switching elements is electrically connected. The first and second busbars are toothed and the semiconductor switching elements are arranged on the teeth, the teeth being arranged alternately. The third busbar is arranged above the semiconductor switching elements, and a heat sink is arranged below the first and second busbars.

Abstract: A half-bridge switch arrangement includes a high-side switch having a plurality of parallel-connected first semiconductor switching elements, a low-side switch having a plurality of parallel-connected second semiconductor switching elements, a positive busbar connected to a first terminal of each of the first semiconductor switching elements, a negative busbar connected to a second terminal of each of the second semiconductor switching elements, and a heat sink arranged between a first section of the positive busbar and a first section of the negative busbar, wherein an outer surface of each of the first semiconductor switching elements is in thermal contact with a surface of the first section of the positive busbar facing away from the heat sink, and wherein an outer surface of each of the second semiconductor switching elements is in thermal contact with a surface of the first section of the negative busbar facing away from the heat sink.

Abstract: A power semiconductor device includes a first contact, a second contact, and a semiconductor volume disposed between the first contact and the second contact. The semiconductor volume includes an n-doped field stop layer configured to spatially delimit an electric field that in the semiconductor volume during operation of the power semiconductor device, a heavily p-doped zone and a neighboring heavily n-doped zone, which together form a tunnel diode. The tunnel diode is located in the vicinity of, or adjacent to, or within the field stop layer. The tunnel diode is configured to provide protection against damage to the device due to a rise of an electron flow in an abnormal operating condition, by the fast provision of holes. Further, a method for producing such devices is provided.

Abstract: A power semiconductor device includes a first contact, a second contact, and a semiconductor volume disposed between the first contact and the second contact. The semiconductor volume includes an n-doped field stop layer configured to spatially delimit an electric field that in the semiconductor volume during operation of the power semiconductor device, a heavily p-doped zone and a neighboring heavily n-doped zone, which together form a tunnel diode. The tunnel diode is located in the vicinity of, or adjacent to, or within the field stop layer. The tunnel diode is configured to provide protection against damage to the device due to a rise of an electron flow in an abnormal operating condition, by the fast provision of holes. Further, a method for producing such devices is provided.