Patents by Inventor Eric Pettus

Eric Pettus has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Efficient extraction for colorless multi patterning
    Patent number: 9690897
    Abstract: A method for parasitic capacitance extraction for integrated circuit (IC) designs fabricated involving multiple patterning that includes identifying, at a computing system, metal features in a metal layer of an IC design and generating, at the computing system, a graph based on spacing relationships between the metal features. The method further includes predicting, at the computing system, which metal features are to be formed by the same mask in the multiple patterning lithography process from the graph. The method further can include performing, at the computing system, a parasitic capacitance extraction analysis of the IC design utilizing the prediction of which metal features are to be formed by the same mask, and performing, at the computing system, timing analysis on the IC design utilizing the list of vertices sharing the same designators and the parasitic capacitance extraction calculations.
    Type: Grant
    Filed: February 27, 2014
    Date of Patent: June 27, 2017
    Assignee: NXP USA, INC.
    Inventors: Puneet Sharma, Eric Pettus
  • EFFICIENT EXTRACTION FOR COLORLESS MULTI PATTERNING
    Publication number: 20150242561
    Abstract: A method for parasitic capacitance extraction for integrated circuit (IC) designs fabricated involving multiple patterning that includes identifying, at a computing system, metal features in a metal layer of an IC design and generating, at the computing system, a graph based on spacing relationships between the metal features. The method further includes predicting, at the computing system, which metal features are to be formed by the same mask in the multiple patterning lithography process from the graph. The method further can include performing, at the computing system, a parasitic capacitance extraction analysis of the IC design utilizing the prediction of which metal features are to be formed by the same mask, and performing, at the computing system, timing analysis on the IC design utilizing the list of vertices sharing the same designators and the parasitic capacitance extraction calculations.
    Type: Application
    Filed: February 27, 2014
    Publication date: August 27, 2015
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Puneet Sharma, Eric Pettus