Abstract: A controller is disclosed for a voltage regulator module including a power unit and providing an output current, Iout, at an output voltage, Vout, from an input current/voltage and being configured for use in a multi-module voltage regulator having a neighbouring voltage regulator module having a respective output connected in parallel, the controller comprising: a reference voltage source for providing a reference voltage; a current balancing unit, configured to receive a respective output current from the or each neighbouring voltage regulator module and to determine an adjusted reference voltage, from the reference voltage and for balancing the output current with the at least one respective output current; and a control unit configured to use the adjusted reference voltage to control the voltage regulator module, to provide the output current at the output voltage from the input current at the input voltage, based on adaptive voltage positioning regulation.

Abstract: A power management integrated circuit comprises a modular interleaved clock generator comprising a plurality of interconnected modular elements, each element constructed to generate and output a clock signal, and each one comprising: a phase port high input; a phase port low input; a clock input; and a bypass switch coupled between the phase port high input and the phase port low input, wherein in response to the bypass switch of at least one of the plurality of elements in a closed state, the phase port high inputs or the phase port low inputs of the remaining elements absent the at least one interleaving controller having the bypass switch in the closed state each receives a voltage that interleaves the clock signals output from the remaining active elements to have an interleaving arrangement that includes equal phase delays.

Abstract: A controller for a switched mode power converter (SMPC) module for use in a multiphase SCMP is disclosed, comprising: a signal generator, configured to generate a periodic signal and a clock, both having a frequency and a signal phase, and for controlling the switched mode power converter module; a first-clock and second-clock inputs configured to receive respective first-clock and second-clock signal having the frequency and respective first and second phases from neighbouring controllers; and wherein the signal generator comprises a phase adjustment circuit configured to adjust the phase of the periodic signal so as to be equidistant from the first and second phase, wherein the phase adjustment circuit determines an error signal in dependence on an offset between the phase and a mid-point between the first phase and the second phase, and a feedback circuit configured to adjust the phase in dependence on the error signal.

Abstract: A power management integrated circuit comprises a modular interleaved clock generator comprising a plurality of interconnected modular elements, each element constructed to generate and output a clock signal, and each one comprising: a phase port high input; a phase port low input; a clock input; and a bypass switch coupled between the phase port high input and the phase port low input, wherein in response to the bypass switch of at least one of the plurality of elements in a closed state, the phase port high inputs or the phase port low inputs of the remaining elements absent the at least one interleaving controller having the bypass switch in the closed state each receives a voltage that interleaves the clock signals output from the remaining active elements to have an interleaving arrangement that includes equal phase delays.

Abstract: A controller is disclosed for a voltage regulator module including a power unit and providing an output current, Iout, at an output voltage, Vout, from an input current/voltage and being configured for use in a multi-module voltage regulator having a neighbouring voltage regulator module having a respective output connected in parallel, the controller comprising: a reference voltage source for providing a reference voltage; a current balancing unit, configured to receive a respective output current from the or each neighbouring voltage regulator module and to determine an adjusted reference voltage, from the reference voltage and for balancing the output current with the at least one respective output current; and a control unit configured to use the adjusted reference voltage to control the voltage regulator module, to provide the output current at the output voltage from the input current at the input voltage, based on adaptive voltage positioning regulation.

Abstract: A controller for a switched mode power converter (SMPC) module for use in a multiphase SCMP is disclosed, comprising: a signal generator, configured to generate a periodic signal and a clock, both having a frequency and a signal phase, and for controlling the switched mode power converter module; a first-clock and second-clock inputs configured to receive respective first-clock and second-clock signal having the frequency and respective first and second phases from neighbouring controllers; and wherein the signal generator comprises a phase adjustment circuit configured to adjust the phase of the periodic signal so as to be equidistant from the first and second phase, wherein the phase adjustment circuit determines an error signal in dependence on an offset between the phase and a mid-point between the first phase and the second phase, and a feedback circuit configured to adjust the phase in dependence on the error signal.

Abstract: An integrated circuit comprising: an input terminal configured to receive a failure-event-signal representative of a failure event; a first output terminal configured to provide a first-failure-signal; and a second output terminal configured to provide a second-failure-signal; and a processing block configured to: set the first-failure-signal based on the failure-event-signal; and set the second-failure-signal, at a predetermined time interval after the first-failure-signal is set. The processing block further comprises a switch configured selectively, based on a received digital-error-signal to either: set the second-failure-signal based on a digital-counter-output-signal; or set the second-failure-signal based on an analogue-trigger-signal.

Abstract: An ESD protection circuit and device structure comprises five transistors, two PNP and three NPN. The five transistors are coupled together so that a first NPN and PNP pair constitute a first silicon controlled rectifier, SCR. The NPN transistor 102 of the first SCR and a third transistor of NPN type are coupled so that they constitute a Darlington pair. A further NPN and PNP pair are coupled together to form a second SCR with the collector of the PNP transistor of the first SCR being coupled with the emitter of the PNP transistor of the second SCR. The circuit is particularly suitable for high voltage triggering applications and two or more devices may be cascaded in series in order to further increase the triggering voltage.

Abstract: An integrated circuit comprising: an input terminal configured to receive a failure-event-signal representative of a failure event; a first output terminal configured to provide a first-failure-signal; and a second output terminal configured to provide a second-failure-signal; and a processing block configured to: set the first-failure-signal based on the failure-event-signal; and set the second-failure-signal, at a predetermined time interval after the first-failure-signal is set. The processing block further comprises a switch configured selectively, based on a received digital-error-signal to either: set the second-failure-signal based on a digital-counter-output-signal; or set the second-failure-signal based on an analogue-trigger-signal.

Abstract: An ESD protection circuit and device structure comprises five transistors, two PNP and three NPN. The five transistors are coupled together so that a first NPN and PNP pair constitute a first silicon controlled rectifier, SCR. The NPN transistor 102 of the first SCR and a third transistor of NPN type are coupled so that they constitute a Darlington pair. A further NPN and PNP pair are coupled together to form a second SCR with the collector of the PNP transistor of the first SCR being coupled with the emitter of the PNP transistor of the second SCR. The circuit is particularly suitable for high voltage triggering applications and two or more devices may be cascaded in series in order to further increase the triggering voltage.

Abstract: A detection circuit for an alternator regulator, and method therefor. The detection circuit comprises an input circuit arranged to receive a phase signal from an alternator regulator and to output an attenuated sense signal representative of the received phase signal, a detection component operably coupled to the input circuit and arranged to receive the attenuated sense signal output by the input circuit, and a blocking capacitance operably coupled between the input circuit and the detection component and arranged to block a DC component of the attenuated sense signal. The detection component is arranged to compare the received attenuated sense signal to at least one reference voltage signal, and to output a signal representative of a frequency of the phase signal from the alternator regulator based at least partly on the comparison of the received attenuated sense signal to the at least one reference voltage signal.

Abstract: A detection circuit for an alternator regulator, and method therefor. The detection circuit comprises an input circuit arranged to receive a phase signal from an alternator regulator and to output an attenuated sense signal representative of the received phase signal, a detection component operably coupled to the input circuit and arranged to receive the attenuated sense signal output by the input circuit, and a blocking capacitance operably coupled between the input circuit and the detection component and arranged to block a DC component of the attenuated sense signal. The detection component is arranged to compare the received attenuated sense signal to at least one reference voltage signal, and to output a signal representative of a frequency of the phase signal from the alternator regulator based at least partly on the comparison of the received attenuated sense signal to the at least one reference voltage signal.