Patents by Inventor Eric Pihet
Eric Pihet has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11567892Abstract: In accordance with an embodiment, an integrated driver circuit includes: a first connection and a second connection configured to be connected to a control chip; at least one bus connection configured to be connected to a bus line; and a control circuit. The control circuit is configured to operate in a first mode or a second mode; to output a reception signal at the second connection in the second mode, where the reception signal represents a bus signal received at the bus connection; to assume a state of low power consumption in the first mode; to change from the first mode to the second mode when a first command is detected at the first connection or at the second connection; and to change from the second mode to the first mode when the bus signal does not indicate any data for a predefined period of time.Type: GrantFiled: April 14, 2021Date of Patent: January 31, 2023Assignee: Infineon Technologies AGInventors: Tobias Islinger, Magnus-Maria Hell, Maximilian Mangst, Eric Pihet, Jens Repp
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Patent number: 11374758Abstract: A transceiver is disclosed including a transmitter designed to output a first signal according to a physical communication protocol, and to output a second signal comprising at least one cryptographic datum. The first and the second signal may be overlaid onto one another as an overlay signal at the output of the transceiver, and may comply with the physical communication protocol. The overlay signal may be received and processed by a receiver.Type: GrantFiled: April 26, 2019Date of Patent: June 28, 2022Assignee: Infineon Technologies AGInventors: Alexander Zeh, Vivin Richards Allimuthu Elavarasu, Eric Pihet
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Publication number: 20220123958Abstract: A transmitter circuit for a field bus driver includes a first bus terminal and a second bus terminal for connecting a first bus line and, respectively, a second bus line. The transmitter circuit further includes a first supply terminal for receiving a supply voltage and second supply terminal for receiving a reference voltage, a first switching circuit coupled between the first supply terminal and the first bus terminal, and a second switching circuit coupled between the second bus terminal and the second supply terminal. The first switching circuit includes a first transistor and a second transistor, and the second switching circuit includes a third transistor and a fourth transistor. Further, the transmitter circuit comprises control circuitry configured to generate first drive signals for the first transistor and the third transistor and second drive signals for the second transistor and the fourth transistor based on a transmit signal.Type: ApplicationFiled: September 7, 2021Publication date: April 21, 2022Inventors: Jens Repp, Thorsten Hinderer, Maximilian Mangst, Eric Pihet
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Publication number: 20210334232Abstract: In accordance with an embodiment, an integrated driver circuit includes: a first connection and a second connection configured to be connected to a control chip; at least one bus connection configured to be connected to a bus line; and a control circuit. The control circuit is configured to operate in a first mode or a second mode; to output a reception signal at the second connection in the second mode, where the reception signal represents a bus signal received at the bus connection; to assume a state of low power consumption in the first mode; to change from the first mode to the second mode when a first command is detected at the first connection or at the second connection; and to change from the second mode to the first mode when the bus signal does not indicate any data for a predefined period of time.Type: ApplicationFiled: April 14, 2021Publication date: October 28, 2021Inventors: Tobias Islinger, Magnus-Maria Hell, Maximilian Mangst, Eric Pihet, Jens Repp
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Patent number: 10728064Abstract: A method for a bus interface circuit is described. According to one exemplary embodiment, the method comprises coding a first data stream by assigning first symbols to falling and rising edges of the first data stream, and coding a further data stream by assigning second symbols to the edges or levels of said further data stream. A symbol sequence is constructed from the first symbols and second symbols, wherein said symbol sequence is constructed in such a manner that the first symbols are always delayed by the same value relative to the associated edges of the first data stream. The method also comprises transmitting the symbol sequence via a galvanically isolating component, and decoding the symbol sequence transmitted via the galvanically isolating component in order to reconstruct the first data stream and the further data stream.Type: GrantFiled: March 7, 2019Date of Patent: July 28, 2020Assignee: Infineon Technologies AGInventors: Maximilian Mangst, Eric Pihet, Thorsten Hinderer
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Patent number: 10592456Abstract: Systems, devices, methods, and techniques for bus receivers operable to provide a data output corresponding to a voltage differential provided on a two-conductor data bus. In one example, a bus receiver comprises a four-quadrant input circuit and a gain stage coupled to the four-quadrant input circuit. In various examples, the four-quadrant input circuit is operable to provide common mode current compensation based on a common mode voltage present on the two-conductor data bus.Type: GrantFiled: August 1, 2018Date of Patent: March 17, 2020Assignee: Infineon Technologies AGInventors: Thorsten Hinderer, David Astrom, Eric Pihet
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Publication number: 20190334720Abstract: A transceiver is disclosed including a transmitter designed to output a first signal according to a physical communication protocol, and to output a second signal comprising at least one cryptographic datum. The first and the second signal may be overlaid onto one another as an overlay signal at the output of the transceiver, and may comply with the physical communication protocol. The overlay signal may be received and processed by a receiver.Type: ApplicationFiled: April 26, 2019Publication date: October 31, 2019Inventors: Alexander Zeh, Vivin Richards Allimuthu Elavarasu, Eric Pihet
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Publication number: 20190288886Abstract: A method for a bus interface circuit is described. According to one exemplary embodiment, the method comprises coding a first data stream by assigning first symbols to falling and rising edges of the first data stream, and coding a further data stream by assigning second symbols to the edges or levels of said further data stream. A symbol sequence is constructed from the first symbols and second symbols, wherein said symbol sequence is constructed in such a manner that the first symbols are always delayed by the same value relative to the associated edges of the first data stream. The method also comprises transmitting the symbol sequence via a galvanically isolating component, and decoding the symbol sequence transmitted via the galvanically isolating component in order to reconstruct the first data stream and the further data stream.Type: ApplicationFiled: March 7, 2019Publication date: September 19, 2019Inventors: Maximilian Mangst, Eric Pihet, Thorsten Hinderer
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Publication number: 20180341615Abstract: Systems, devices, methods, and techniques for bus receivers operable to provide a data output corresponding to a voltage differential provided on a two-conductor data bus. In one example, a bus receiver comprises a four-quadrant input circuit and a gain stage coupled to the four-quadrant input circuit. In various examples, the four-quadrant input circuit is operable to provide common mode current compensation based on a common mode voltage present on the two-conductor data bus.Type: ApplicationFiled: August 1, 2018Publication date: November 29, 2018Inventors: Thorsten Hinderer, David Astrom, Eric Pihet
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Patent number: 10120434Abstract: A semiconductor device is described herein. In accordance with one exemplary embodiment the semiconductor device includes a chip package, which includes at least one semiconductor chip, a dedicated ground pin, a first supply pin for receiving a first supply voltage, a second supply pin for receiving a second supply voltage, and a first input pin. The semiconductor device further includes a first circuit integrated in the semiconductor chip, wherein the first circuit is coupled to the first supply pin and to the ground pin, and a second circuit integrated in the semiconductor chip, wherein the second circuit is coupled to the first supply pin and to a virtual ground node. An electronic switch is configured to connect the virtual ground node with the first input pin dependent on the level of a first input signal.Type: GrantFiled: May 13, 2016Date of Patent: November 6, 2018Assignee: Infineon Technologies AGInventor: Eric Pihet
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Patent number: 10042807Abstract: Systems, devices, methods, and techniques for bus receivers operable to provide a data output corresponding to a voltage differential provided on a two-conductor data bus. In one example, a bus receiver comprises a four-quadrant input circuit and a gain stage coupled to the four-quadrant input circuit. In various examples, the four-quadrant input circuit is operable to provide common mode current compensation based on a common mode voltage present on the two-conductor data bus.Type: GrantFiled: April 5, 2016Date of Patent: August 7, 2018Assignee: Infineon Technologies AGInventors: Thorsten Hinderer, David Astrom, Eric Pihet
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Patent number: 9965426Abstract: According to various embodiments, a method of operating a two-wire digital bus includes applying a bias voltage to the two-wire digital bus at a first interface node, measuring a common mode voltage of the two-wire digital bus at the first interface node, and adjusting the bias voltage at the first interface node based on the measured common mode voltage.Type: GrantFiled: January 7, 2015Date of Patent: May 8, 2018Assignee: INFINEON TECHNOLOGIES AGInventor: Eric Pihet
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Publication number: 20170329388Abstract: A semiconductor device is described herein. In accordance with one exemplary embodiment the semiconductor device includes a chip package, which includes at least one semiconductor chip, a dedicated ground pin, a first supply pin for receiving a first supply voltage, a second supply pin for receiving a second supply voltage, and a first input pin. The semiconductor device further includes a first circuit integrated in the semiconductor chip, wherein the first circuit is coupled to the first supply pin and to the ground pin, and a second circuit integrated in the semiconductor chip, wherein the second circuit is coupled to the first supply pin and to a virtual ground node. An electronic switch is configured to connect the virtual ground node with the first input pin dependent on the level of a first input signal.Type: ApplicationFiled: May 13, 2016Publication date: November 16, 2017Inventor: Eric Pihet
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Publication number: 20170286347Abstract: Systems, devices, methods, and techniques are disclosed for bus receivers operable to provide a data output corresponding to a voltage differential provided on a two-conductor data bus. In one example, a bus receiver comprises a four-quadrant input circuit and a gain stage coupled to the four-quadrant input circuit. In various examples, the four-quadrant input circuit is operable to provide common mode current compensation based on a common mode voltage present on the two-conductor data bus.Type: ApplicationFiled: April 5, 2016Publication date: October 5, 2017Inventors: Thorsten Hinderer, David Astrom, Eric Pihet
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Publication number: 20160196230Abstract: According to various embodiments, a method of operating a two-wire digital bus includes applying a bias voltage to the two-wire digital bus at a first interface node, measuring a common mode voltage of the two-wire digital bus at the first interface node, and adjusting the bias voltage at the first interface node based on the measured common mode voltage.Type: ApplicationFiled: January 7, 2015Publication date: July 7, 2016Inventor: Eric Pihet
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Patent number: 7888969Abstract: A driver circuit and method for generating two complementary output currents from a two-state logic input signal at two outputs for connecting a two-wire conductor provide the following actions: generating from the input signal, an output signal at each output, the amperage of one of the output currents being adjustable by a control signal; analyzing each voltage materializing at the outputs; generating an error signal as a function of the output voltages within each of at least two time slots subsequent to a change in state of the input signal; caching the error signals or signals derived therefrom and adjusting, as a function of cached error signals or of the cached signals as a function thereof, the output current in corresponding time slots subsequent to a resulting change in state of the input signal.Type: GrantFiled: January 19, 2010Date of Patent: February 15, 2011Assignee: Infineon Technologies AGInventors: Dieter Metzner, Eric Pihet
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Publication number: 20100201399Abstract: A driver circuit and method for generating two complementary output currents from a two-state logic input signal at two outputs for connecting a two-wire conductor provide the following actions: generating from the input signal, an output signal at each output, the amperage of one of the output currents being adjustable by a control signal; analyzing each voltage materializing at the outputs; generating an error signal as a function of the output voltages within each of at least two time slots subsequent to a change in state of the input signal; caching the error signals or signals derived therefrom and adjusting, as a function of cached error signals or of the cached signals as a function thereof, the output current in corresponding time slots subsequent to a resulting change in state of the input signal.Type: ApplicationFiled: January 19, 2010Publication date: August 12, 2010Inventors: Dieter Metzner, Eric Pihet
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Patent number: 7178070Abstract: The invention relates to a method for monitoring a microcontroller having at least one normal operating state and one state with a reduced power consumption and to a circuit configuration for carrying out the method. The method enables the functionality of the microcontroller to be monitored even in the state with the reduced power consumption. The method includes steps of: during the normal operating state, receiving a status signal having pulses from the microcontroller and resetting the microcontroller if the pulses are not received within a predefined time pattern; and during the state with the reduced power consumption, transmitting a wakeup signal having a sequence of pulses to the microcontroller, and resetting the microcontroller if there is no confirmation by the microcontroller within a predefined time interval after a pulse of the wakeup signal.Type: GrantFiled: May 28, 2003Date of Patent: February 13, 2007Assignee: Infineon Technologies AGInventors: Eric Pihet, Josef Gerner
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Patent number: 7053592Abstract: A circuit configuration provides an output voltage from an input voltage. The circuit configuration has a voltage regulator with an input terminal for receiving an input voltage, an output terminal for providing an output voltage, and drive input for receiving a drive signal. A drive circuit is coupled to the drive input and switches the voltage regulator on and off in a clocked manner according to a state signal.Type: GrantFiled: May 28, 2003Date of Patent: May 30, 2006Assignee: Infineon Technologies AGInventors: Eric Pihet, Josef Gerner
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Patent number: 6948847Abstract: A temperature sensor for a MOS circuit configuration is implemented as the gate of a MOS transistor and configured as a two-terminal network with a gate input and a gate output. By measuring the voltage drop across gate it is possible to determine the temperature at its location.Type: GrantFiled: May 8, 2003Date of Patent: September 27, 2005Assignee: Infineon Technologies AGInventors: Eric Pihet, Michael Glavanovics, Thomas Krotscheck, Rudolf Zelsacher