Abstract: A processor (100) is provided that is a programmable fixed point digital signal processor (DSP) with variable instruction length, offering both high code density and easy programming. Architecture and instruction set are optimized for low power consumption and high efficiency execution of DSP algorithms, such as for wireless telephones, as well as pure control tasks. The processor includes an instruction buffer unit (106), a program flow control unit (108), an address/data flow unit (110), a data computation unit (112), and multiple interconnecting busses. Dual multiply-accumulate blocks improve processing performance. A memory interface unit (104) provides parallel access to data and instruction memories. The instruction buffer is operable to buffer single and compound instructions pending execution thereof. A decode mechanism is configured to decode instructions from the instruction buffer. The use of compound instructions enables effective use of the bandwidth available within the processor.

Abstract: A processor (100) is provided that is a programmable digital signal processor (DSP) with variable instruction length, offering both high code density and easy programming. Instructions may be executed during delay slots after program branching while an execution pipeline is being restarted. Architecture and instruction set are optimized for low power consumption and high efficiency execution of DSP algorithms, such as for wireless telephones, as well as pure control tasks. A software breakpoint instruction is provided for debugging purposes. In order to correctly emulate the operation of the instruction pipeline when a software breakpoint instruction is executed during a delay slot, the width (1110-1115) of the software breakpoint is the same as the replaced instruction. A limited number of breakpoint instruction length formats (1100, 1102) are combined with non-operational instructions (NOP, NOP—16) to form a large number of combination instructions that match any instruction length format.

Abstract: A layout system (10) includes a place and route tool (12) and a datapath layout generator. The datapath layout generator (14) provides a mechanism for the designer to place datapath cells in a structured arrangement. The datapath layout generator (14) sends a language configuration file to the place and route tool (12) to install the datapath structure. The datapath structure assigned “fixed” status, which prevents the place and route tool (12) from moving the datapath cells in later operations. Constraints for the remaining cells are then installed in the place and route tool (12), and criteria-driven placement, such as timing-driven placement, can be used to arrange these cells in an optimum fashion. The remaining cells can be placed in open areas of the datapath structure for improved density.