Abstract: We report methods relating to scan warmup of integrated circuit devices. One such method may comprise loading a scan test stimulus to and unloading a scan test response from a first set of logic elements of an integrated circuit device at a scan clock first frequency equal to a test clock frequency; adjusting the scan clock from the first frequency to a second frequency by a scan warmup unit, wherein the scan clock second frequency is equal to a system clock frequency; and capturing the scan test response by a shift logic at the scan clock second frequency. We also report processors containing components configured to implement the method, and fabrication of such processors. The methods and their implementation may reduce di/dt events otherwise commonly occurring when testing logic elements of integrated circuit devices.

Abstract: Methods relating to distribution of a clock signal to logic devices of an integrated circuit. The method includes controlling, by a logic element, the distribution of a clock signal by a clock gater and distributing the clock signal by the clock gater to at least one first logic device, wherein the logic element allows the first clock gater to distribute the clock signal only when at least one first logic device requires the clock signal. An integrated circuit configured to perform such a method. Fabrication of such an integrated circuit.

Abstract: We report methods relating to scan warmup of integrated circuit devices. One such method may comprise loading a scan test stimulus to and unloading a scan test response from a first set of logic elements of an integrated circuit device at a scan clock first frequency equal to a test clock frequency; adjusting the scan clock from the first frequency to a second frequency by a scan warmup unit, wherein the scan clock second frequency is equal to a system clock frequency; and capturing the scan test response by a shift logic at the scan clock second frequency. We also report processors containing components configured to implement the method, and fabrication of such processors. The methods and their implementation may reduce di/dt events otherwise commonly occurring when testing logic elements of integrated circuit devices.

Abstract: Methods relating to distribution of a clock signal to logic devices of an integrated circuit. The method includes controlling, by a logic element, the distribution of a clock signal by a dock gater and distributing the clock signal by the clock gater to at least one first logic device, wherein the logic element allows the first clock gater to distribute the clock signal only when at least one first logic device requires the clock signal. An integrated circuit configured to perform such a method. Fabrication of such an integrated circuit.

Abstract: A semiconductor device includes a primary voltage rail, a secondary voltage rail, a plurality of transistors coupled between the primary and secondary voltage rails, and control logic operable to enable a first subset of the plurality of transistors to couple the primary voltage rail to the secondary voltage rail. During a steady state condition, the first subset comprises less than all of the plurality of transistors.

Abstract: A semiconductor device includes a primary voltage rail, a secondary voltage rail, a plurality of transistors coupled between the primary and secondary voltage rails, and control logic operable to enable a first subset of the plurality of transistors to couple the primary voltage rail to the secondary voltage rail. During a steady state condition, the first subset comprises less than all of the plurality of transistors.

Abstract: A bridge fused multiply-adder is disclosed. The fused multiply-adder is for the single instruction execution of (A×B)+C. The bridge fused multiply-add unit adds this functionality to existing floating-point co-processor units by including a fused multiply-add hardware “bridge” between an existing floating-point adder and a floating-point multiplier unit. This fused multiply-add functionality is added to existing two-operand architecture designs without degrading the performance or parallel pipe execution of floating-point adder and floating-point multiplier instructions.

Abstract: A three-path floating-point fused multiply-adder is disclosed. The fused multiply-adder is for the single instruction execution of (A×B)+C. The three-path fused multiply-adder is based on a dual-path adder and reduces latency significantly by operating on case data in parallel and by reducing component bit size. The fused multiply-adder is a common serial fused multiply-adder that reuses floating-point adder (FPA) and floating-point multiplier (FPM) hardware, allowing single adds, single multiplies, and fused multiply-adds to execute at maximum speed.

Abstract: A three-path floating-point fused multiply-adder is disclosed. The fused multiply-adder is for the single instruction execution of (A×B)+C. The three-path fused multiply-adder is based on a dual-path adder and reduces latency significantly by operating on case data in parallel and by reducing component bit size. The fused multiply-adder is a common serial fused multiply-adder that reuses floating-point adder (FPA) and floating-point multiplier (FPM) hardware, allowing single adds, single multiplies, and fused multiply-adds to execute at maximum speed.

Abstract: A bridge fused multiply-adder is disclosed. The fused multiply-adder is for the single instruction execution of (A×B)+C. The bridge fused multiply-add unit adds this functionality to existing floating-point co-processor units by including a fused multiply-add hardware “bridge” between an existing floating-point adder and a floating-point multiplier unit. This fused multiply-add functionality is added to existing two-operand architecture designs without degrading the performance or parallel pipe execution of floating-point adder and floating-point multiplier instructions.