Patents by Inventor Eric R. Blomiley

Eric R. Blomiley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10147727
    Abstract: Some embodiments include a conductive structure which has a first conductive material having a work function of at least 4.5 eV, and a second conductive material over and directly against the first conductive material. The second conductive material has a work function of less than 4.5 eV, and is shaped as an upwardly-opening container. The conductive structure includes a third conductive material within the upwardly-opening container shape of the second conductive material and directly against the second conductive material. The third conductive material is a different composition relative to the second conductive material. Some embodiments include wordlines, and some embodiments include transistors.
    Type: Grant
    Filed: February 13, 2018
    Date of Patent: December 4, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Jaydeb Goswami, Zailong Bian, Yushi Hu, Eric R. Blomiley, Jaydip Guha, Thomas Gehrke
  • Publication number: 20180175039
    Abstract: Some embodiments include a conductive structure which has a first conductive material having a work function of at least 4.5 eV, and a second conductive material over and directly against the first conductive material. The second conductive material has a work function of less than 4.5 eV, and is shaped as an upwardly-opening container. The conductive structure includes a third conductive material within the upwardly-opening container shape of the second conductive material and directly against the second conductive material. The third conductive material is a different composition relative to the second conductive material. Some embodiments include wordlines, and some embodiments include transistors.
    Type: Application
    Filed: February 13, 2018
    Publication date: June 21, 2018
    Applicant: Micron Technology, Inc.
    Inventors: Jaydeb Goswami, Zailong Bian, Yushi Hu, Eric R. Blomiley, Jaydip Guha, Thomas Gehrke
  • Publication number: 20180138182
    Abstract: Some embodiments include a conductive structure which has a first conductive material having a work function of at least 4.5 eV, and a second conductive material over and directly against the first conductive material. The second conductive material has a work function of less than 4.5 eV, and is shaped as an upwardly-opening container. The conductive structure includes a third conductive material within the upwardly-opening container shape of the second conductive material and directly against the second conductive material. The third conductive material is a different composition relative to the second conductive material. Some embodiments include wordlines, and some embodiments include transistors.
    Type: Application
    Filed: November 11, 2016
    Publication date: May 17, 2018
    Inventors: Jaydeb Goswami, Zailong Bian, Yushi Hu, Eric R. Blomiley, Jaydip Guha, Thomas Gehrke
  • Patent number: 9972628
    Abstract: Some embodiments include a conductive structure which has a first conductive material having a work function of at least 4.5 eV, and a second conductive material over and directly against the first conductive material. The second conductive material has a work function of less than 4.5 eV, and is shaped as an upwardly-opening container. The conductive structure includes a third conductive material within the upwardly-opening container shape of the second conductive material and directly against the second conductive material. The third conductive material is a different composition relative to the second conductive material. Some embodiments include wordlines, and some embodiments include transistors.
    Type: Grant
    Filed: November 11, 2016
    Date of Patent: May 15, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Jaydeb Goswami, Zailong Bian, Yushi Hu, Eric R. Blomiley, Jaydip Guha, Thomas Gehrke
  • Patent number: 8426919
    Abstract: Some embodiments include formation of at least one cavity in a first semiconductor material, followed by epitaxially growing a second semiconductor material over the first semiconductor material and bridging across the at least one cavity. The cavity may be left open, or material may be provided within the cavity. The material provided within the cavity may be suitable for forming, for example, one or more of electromagnetic radiation interaction components, transistor gates, insulative structures, and coolant structures. Some embodiments include one or more of transistor devices, electromagnetic radiation interaction components, transistor devices, coolant structures, insulative structures and gas reservoirs.
    Type: Grant
    Filed: April 28, 2011
    Date of Patent: April 23, 2013
    Assignee: Micron Technology, Inc.
    Inventors: David H. Wells, Eric R. Blomiley
  • Patent number: 8216935
    Abstract: A method of forming a transistor gate construction includes forming a gate stack comprising a sacrificial material received over conductive gate material. The gate stack has lateral sidewalls having insulative material received there-against. The sacrificial material is removed from being received over the conductive gate material to form a void space between the insulative material over the conductive gate material. Elemental tungsten is selectively deposited within the void space over the conductive gate material and a transistor gate construction forming there-from is formed there-from, and which has a conductive gate electrode which includes the conductive gate material and the elemental tungsten. The transistor gate might be used in NAND, DRAM, or other integrated circuitry.
    Type: Grant
    Filed: April 7, 2009
    Date of Patent: July 10, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Eric R. Blomiley, Allen McTeer
  • Patent number: 8035129
    Abstract: This invention includes methods of forming layers comprising epitaxial silicon, and field effect transistors. In one implementation, a method of forming a layer comprising epitaxial silicon comprises epitaxially growing a silicon-comprising layer from an exposed monocrystalline material. The epitaxially grown silicon comprises at least one of carbon, germanium, and oxygen present at a total concentration of no greater than 1 atomic percent. In one implementation, the layer comprises a silicon germanium alloy comprising at least 1 atomic percent germanium, and further comprises at least one of carbon and oxygen at a total concentration of no greater than 1 atomic percent. Other aspects and implementations are contemplated.
    Type: Grant
    Filed: June 22, 2010
    Date of Patent: October 11, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Nirmal Ramaswamy, Gurtej S. Sandhu, Cem Basceri, Eric R. Blomiley
  • Publication number: 20110210400
    Abstract: Some embodiments include formation of at least one cavity in a first semiconductor material, followed by epitaxially growing a second semiconductor material over the first semiconductor material and bridging across the at least one cavity. The cavity may be left open, or material may be provided within the cavity. The material provided within the cavity may be suitable for forming, for example, one or more of electromagnetic radiation interaction components, transistor gates, insulative structures, and coolant structures. Some embodiments include one or more of transistor devices, electromagnetic radiation interaction components, transistor devices, coolant structures, insulative structures and gas reservoirs.
    Type: Application
    Filed: April 28, 2011
    Publication date: September 1, 2011
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: David H. Wells, Eric R. Blomiley
  • Patent number: 7956416
    Abstract: Some embodiments include formation of at least one cavity in a first semiconductor material, followed by epitaxially growing a second semiconductor material over the first semiconductor material and bridging across the at least one cavity. The cavity may be left open, or material may be provided within the cavity. The material provided within the cavity may be suitable for forming, for example, one or more of electromagnetic radiation interaction components, transistor gates, insulative structures, and coolant structures. Some embodiments include one or more of transistor devices, electromagnetic radiation interaction components, transistor devices, coolant structures, insulative structures and gas reservoirs.
    Type: Grant
    Filed: May 29, 2009
    Date of Patent: June 7, 2011
    Assignee: Micron Technology, Inc.
    Inventors: David H. Wells, Eric R. Blomiley
  • Publication number: 20100258857
    Abstract: This invention includes methods of forming layers comprising epitaxial silicon, and field effect transistors. In one implementation, a method of forming a layer comprising epitaxial silicon comprises epitaxially growing a silicon-comprising layer from an exposed monocrystalline material. The epitaxially grown silicon comprises at least one of carbon, germanium, and oxygen present at a total concentration of no greater than 1 atomic percent. In one implementation, the layer comprises a silicon germanium alloy comprising at least 1 atomic percent germanium, and further comprises at least one of carbon and oxygen at a total concentration of no greater than 1 atomic percent. Other aspects and implementations are contemplated.
    Type: Application
    Filed: June 22, 2010
    Publication date: October 14, 2010
    Inventors: Nirmal Ramaswamy, Gurtej S. Sandhu, Cem Basceri, Eric R. Blomiley
  • Publication number: 20100255669
    Abstract: A method of forming a transistor gate construction includes forming a gate stack comprising a sacrificial material received over conductive gate material. The gate stack has lateral sidewalls having insulative material received there-against. The sacrificial material is removed from being received over the conductive gate material to form a void space between the insulative material over the conductive gate material. Elemental tungsten is selectively deposited within the void space over the conductive gate material and a transistor gate construction forming there-from is formed there-from, and which has a conductive gate electrode which includes the conductive gate material and the elemental tungsten. The transistor gate might be used in NAND, DRAM, or other integrated circuitry.
    Type: Application
    Filed: April 7, 2009
    Publication date: October 7, 2010
    Inventors: Eric R. Blomiley, Allen McTeer
  • Patent number: 7768036
    Abstract: This invention includes methods of forming layers comprising epitaxial silicon, and field effect transistors. In one implementation, a method of forming a layer comprising epitaxial silicon comprises epitaxially growing a silicon-comprising layer from an exposed monocrystalline material. The epitaxially grown silicon comprises at least one of carbon, germanium, and oxygen present at a total concentration of no greater than 1 atomic percent. In one implementation, the layer comprises a silicon germanium alloy comprising at least 1 atomic percent germanium, and further comprises at least one of carbon and oxygen at a total concentration of no greater than 1 atomic percent. Other aspects and implementations are contemplated.
    Type: Grant
    Filed: March 24, 2009
    Date of Patent: August 3, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Nirmal Ramaswamy, Gurtej S. Sandhu, Cem Basceri, Eric R. Blomiley
  • Patent number: 7662649
    Abstract: The invention includes deposition apparatuses having reflectors with rugged reflective surfaces configured to disperse light reflected therefrom, and/or having dispersers between lamps and a substrate. The invention also includes optical methods for utilization within a deposition apparatus for assessing the alignment of a substrate within the apparatus and/or for assessing the thickness of a layer of material deposited within the apparatus.
    Type: Grant
    Filed: May 31, 2006
    Date of Patent: February 16, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Eric R. Blomiley, Nirmal Ramaswamy, Ross S. Dando, Joel A. Drewes
  • Publication number: 20090236666
    Abstract: Some embodiments include formation of at least one cavity in a first semiconductor material, followed by epitaxially growing a second semiconductor material over the first semiconductor material and bridging across the at least one cavity. The cavity may be left open, or material may be provided within the cavity. The material provided within the cavity may be suitable for forming, for example, one or more of electromagnetic radiation interaction components, transistor gates, insulative structures, and coolant structures. Some embodiments include one or more of transistor devices, electromagnetic radiation interaction components, transistor devices, coolant structures, insulative structures and gas reservoirs.
    Type: Application
    Filed: May 29, 2009
    Publication date: September 24, 2009
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: David H. Wells, Eric R. Blomiley
  • Patent number: 7585371
    Abstract: In one implementation, a substrate susceptor for receiving a semiconductor substrate for selective epitaxial silicon-comprising depositing thereon, where the depositing comprises measuring emissivity of the susceptor from at least one susceptor location in a non-contacting manner, includes a body having a front substrate receiving side, a back side, and a peripheral edge. At least one susceptor location from which emissivity is to be measured is received on at least one of the front substrate receiving side, the back side, and the edge. Such at least one susceptor location comprises an outermost surface comprising a material upon which selective epitaxial silicon will not deposit upon during selective epitaxial silicon depositing on a semiconductor substrate received by the susceptor for at least an initial thickness of epitaxial silicon depositing on said substrate. Other aspects and implementations are contemplated.
    Type: Grant
    Filed: April 8, 2004
    Date of Patent: September 8, 2009
    Assignee: Micron Technology, Inc.
    Inventors: Eric R. Blomiley, Nirmal Ramaswamy, Ross S. Dando, Joel A. Drewes, Danny Dynka
  • Publication number: 20090179231
    Abstract: This invention includes methods of forming layers comprising epitaxial silicon, and field effect transistors. In one implementation, a method of forming a layer comprising epitaxial silicon comprises epitaxially growing a silicon-comprising layer from an exposed monocrystalline material. The epitaxially grown silicon comprises at least one of carbon, germanium, and oxygen present at a total concentration of no greater than 1 atomic percent. In one implementation, the layer comprises a silicon germanium alloy comprising at least 1 atomic percent germanium, and further comprises at least one of carbon and oxygen at a total concentration of no greater than 1 atomic percent. Other aspects and implementations are contemplated.
    Type: Application
    Filed: March 24, 2009
    Publication date: July 16, 2009
    Inventors: Nirmal Ramaswamy, Gurtej S. Sandhu, Cem Basceri, Eric R. Blomiley
  • Patent number: 7557002
    Abstract: Some embodiments include formation of at least one cavity in a first semiconductor material, followed by epitaxially growing a second semiconductor material over the first semiconductor material and bridging across the at least one cavity. The cavity may be left open, or material may be provided within the cavity. The material provided within the cavity may be suitable for forming, for example, one or more of electromagnetic radiation interaction components, transistor gates, insulative structures, and coolant structures. Some embodiments include one or more of transistor devices, electromagnetic radiation interaction components, transistor devices, coolant structures, insulative structures and gas reservoirs.
    Type: Grant
    Filed: August 18, 2006
    Date of Patent: July 7, 2009
    Assignee: Micron Technology, Inc.
    Inventors: David H. Wells, Eric R. Blomiley
  • Patent number: 7531395
    Abstract: Methods of forming layers comprising epitaxial silicon, and methods of forming field effect transistors are disclosed. A method of forming a layer comprising epitaxial silicon includes etching an opening into a silicate glass-comprising material received over a monocrystalline material. The etching is conducted to the monocrystalline material effective to expose the monocrystalline material at a base of the opening. A silicon-comprising layer is epitaxially grown within the opening from the monocrystalline material exposed at the base of the opening. The silicate glass-comprising material is etched from the substrate effective to leave a free-standing projection of the epitaxially grown silicon-comprising layer projecting from the monocrystalline material which was at the base of the opening. Other implementations and aspects are contemplated.
    Type: Grant
    Filed: January 12, 2005
    Date of Patent: May 12, 2009
    Assignee: Micron Technology, Inc.
    Inventors: Eric R. Blomiley, Gurtej S. Sandhu, Cem Basceri, Nirmal Ramaswamy
  • Patent number: 7528424
    Abstract: This invention includes methods of forming layers comprising epitaxial silicon, and field effect transistors. In one implementation, a method of forming a layer comprising epitaxial silicon comprises epitaxially growing a silicon-comprising layer from an exposed monocrystalline material. The epitaxially grown silicon comprises at least one of carbon, germanium, and oxygen present at a total concentration of no greater than 1 atomic percent. In one implementation, the layer comprises a silicon germanium alloy comprising at least 1 atomic percent germanium, and further comprises at least one of carbon and oxygen at a total concentration of no greater than 1 atomic percent. Other aspects and implementations are contemplated.
    Type: Grant
    Filed: May 4, 2006
    Date of Patent: May 5, 2009
    Assignee: Micron Technology, Inc.
    Inventors: Nirmal Ramaswamy, Gurtej S. Sandhu, Cem Basceri, Eric R. Blomiley
  • Patent number: 7517758
    Abstract: The invention includes methods of forming epitaxial silicon-comprising material and methods of forming vertical transistors. In one implementation, a method of forming epitaxial silicon-comprising material includes providing a substrate comprising monocrystalline material. A first portion of the monocrystalline material is outwardly exposed while a second portion of the monocrystalline material is masked. A first silicon-comprising layer is epitaxially grown from the exposed monocrystalline material of the first portion and not from the monocrystalline material of the masked second portion. After growing the first silicon-comprising layer, the second portion of the monocrystalline material is unmasked. A second silicon-comprising layer is then epitaxially grown from the first silicon-comprising layer and from the unmasked monocrystalline material of the second portion. Other aspects and implementations are contemplated.
    Type: Grant
    Filed: October 20, 2005
    Date of Patent: April 14, 2009
    Assignee: Micron Technology, Inc.
    Inventors: Nirmal Ramaswamy, Gurtej S. Sandhu, Cem Basceri, Eric R. Blomiley