Abstract: An integrated circuit (7A) for multitasking support for processing unit (1A) holds control variables for each task (or activity) to run on its associated processor (1A) and identifies the next task that should run. The circuit (7A) employs level-driven, clock free ripple logic and is configured as a two dimensional array of “tiles”, each tile being composed of simple logic gates and performing a dedicated function. The circuit has particular application to asynchronous multiple processor networks.

Abstract: An integrated circuit (7A) for multitasking support for processing unit (1A) holds control variables for each task (or activity) to run on its associated processor (1A) and identifies the next task that should run. The circuit (7A) employs level-driven, clock free ripple logic and is configured as a two dimensional array of “tiles”, each tile being composed of simple logic gates and performing a dedicated function. The circuit has particular application to asynchronous multiple processor networks.

Abstract: A transparent latch, having a signal input D, an output Q and a control input C for selecting one of two operating modes, functions by either allowing the output to follow the input (in an enable mode) or by blocking any subsequent changes in input signal level (in an inhibit mode). Owing to the design of the latch, relative propagation delays through gates and interconnecting wires cannot cause a wrong value to be latched, this being in contrast with known arrangements. Therefore constraints on the physical layout of the latch are removed. In one embodiment the latch comprises two pairs of NAND gates (5,6,7,8) each pair being connected in a feedback configuration.

Abstract: A multi-processing computer system has multiple computing units. Each of the computing units includes a processor linked to a private memory via a private data bus, and each computing unit is linked to every other computing unit by a respective separate independent shared memory area. The shared memory areas are controlled by a communications controller which can provide a fully asynchronous two-way communication route through the memory area. The multitasking capabilities of the computer are further controlled by a set of unit controllers in combination with respective software task schedulers.

Abstract: A cable closure includes two spaced end plugs (110-110) through which cable nd portions extend and two cover portions (60-60) which are mated together along tongue and groove portions and held together by C-shaped clamps that engage the tongue and groove portions. Conductors of the cables are spliced together and enclosed in a membranous container (40) which subsequently is caused to be filled with an encapsulant. The cover portions, which in a preferred embodiment are identical, include internally disposed plates each having spaced end strap portions which secure the cable end portions extending through the end plugs into the closure at locations external to the membranous container and prevent unintended lateral, longitudinal and torsional movement of the splice work relative to the encapsulant.

Abstract: A termination closure (20) for buried or underground service cable splice locations includes molded stepped end blocks (40--40) and a cover (100) which comprises a sheet adapted to be wrapped about service cables (28--28) having conductors (26--26) which are spliced to conductors (24--24) of a distribution cable (22) and secured by clamps. The closure also includes a pivotally mounted organizer (80) which is perforated to allow an encapsulant to be flowed therethrough into engagement with an enclosing bladder (90). The organizer effectively isolates splice connections from the distribution cable core (23). The bladder which is wrapped about the organizer is adapted to receive encapsulant from a tube which extends through one of the end blocks to allow it to be flowed into the interstices among the spliced conductors and distribution cable core. Air in the closure is pushed from one end of the closure and evacuated through a relief valve (59) in the other end block.