Abstract: A circuit and method for reducing kTC noise in CMOS imagers while minimizing power dissipation is disclosed. Correlated double sampling (CDS) is performed within each pixel such that the reset voltage and the integration voltage are sampled and stored within the pixel until the voltages are forwarded to a differential amplifier for subtraction.

Abstract: Signals from an imager pixel photodetector are received by an amplifier having capacitive feedback, such as a capacitive transimpedance amplifier (CTIA). The amplifier can be operated at a low or no power level during an integration period of a photodetector to reduce power dissipation. The amplifier can be distributed, with an amplifier element within each pixel of an array and with amplifier output circuitry outside the pixel array. The amplifier can be a single ended cascode amplifier, a folded cascode amplifier, a differential input telescopic cascode amplifier, or other configuration. The amplifier can be used in pixel configurations where the amplifier is directly connected to the photodetector, or in configurations which use a transfer transistor to couple signal charges to a floating diffusion node with the amplifier being coupled to the floating diffusion node.

Abstract: A system which operates to determine temperature of an image sensor using the same signal chain that is used to detect the image sensor actual outputs. A correlated double sampling circuit is used to obtain the image outputs. That's same correlated double sampling circuit is used to receive two different inputs from the temperature circuit, and to subtract one from the other. The temperature output can be perceived, for example, once each frame.

Abstract: Operation for global electronic shutter photodiode-type pixels. In a first mode of operation, lag is reduced through global reset of the photodiode array and fixed pattern noise is eliminated through comparison of the photosignal level and the reset level of the floating drain. In a second mode of operation, simultaneous integration and readout processes are achieved through cessation of spill charges over the transfer gate. In a third mode of operation, regulation of the reset photodiode and transfer gate enables voltage gain between the photodiode and the sense node.

Abstract: Signals from an imager pixel photodetector are received by an amplifier having capacitive feedback, such as a capacitive transimpedance amplifier (CTIA). The amplifier can be operated at a low or no power level during an integration period of a photodetector to reduce power dissipation. The amplifier can be distributed, with an amplifier element within each pixel of an array and with amplifier output circuitry outside the pixel array. The amplifier can be a single ended cascode amplifier, a folded cascode amplifier, a differential input telescopic cascode amplifier, or other configuration. The amplifier can be used in pixel configurations where the amplifier is directly connected to the photodetector, or in configurations which use a transfer transistor to couple signal charges to a floating diffusion node with the amplifier being coupled to the floating diffusion node.

Abstract: Designs and operational methods to increase the dynamic range of image sensors and APS devices in particular by achieving more than one integration times for each pixel thereof. An APS system with more than one column-parallel signal chains for readout are described for maintaining a high frame rate in readout. Each active pixel is sampled for multiple times during a single frame readout, thus resulting in multiple integration times. The operation methods can also be used to obtain multiple integration times for each pixel with an APS design having a single column-parallel signal chain for readout. Furthermore, analog-to-digital conversion of high speed and high resolution can be implemented.

Abstract: Signals from an imager pixel photodetector are received by an amplifier having capacitive feedback, such as a capacitive transimpedance amplifier (CTIA). The amplifier can be operated at a low or no power level during an integration period of a photodetector to reduce power dissipation. The amplifier can be distributed, with an amplifier element within each pixel of an array and with amplifier output circuitry outside the pixel array. The amplifier can be a single ended cascode amplifier, a folded cascode amplifier, a differential input telescopic cascode amplifier, or other configuration. The amplifier can be used in pixel configurations where the amplifier is directly connected to the photodetector, or in configurations which use a transfer transistor to couple signal charges to a floating diffusion node with the amplifier being coupled to the floating diffusion node.

Abstract: An imaging device formed as a monolithic complementary metal oxide semiconductor integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate, a readout circuit including at least an output field effect transistor formed in the substrate, and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node connected to the output transistor and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node.

Abstract: Operation for global electronic shutter photodiode-type pixels. In a first mode of operation, lag is reduced through global reset of the photodiode array and fixed pattern noise is eliminated through comparison of the photosignal level and the reset level of the floating drain. In a second mode of operation, simultaneous integration and readout processes are achieved through cessation of spill charges over the transfer gate. In a third mode of operation, regulation of the reset photodiode and transfer gate enables voltage gain between the photodiode and the sense node.

Abstract: A frame shutter apparatus comprising a controller for controlling multiple groups of pixels and for reading out values corresponding to the charge collected by different groups of pixels at different times. A method of reading out multiple groups of pixels is provided wherein values corresponding to the charge collected by one group of pixels is readout at a different time than the values corresponding to the charge collected by another group of pixels.

Abstract: Light sensors having a wide dynamic range are used in a variety of applications. A wide dynamic range light sensor includes an exposed photodiode light transducer accumulating charge in proportion to light incident over an integration period. Sensor logic determines a light integration period prior to the beginning of integration and the charge is reset. Charge accumulated by the exposed light transducer over the light integration period is measured and a pulse having a width based on the accumulated charge is determined.

Abstract: A pixel circuit, and a method for operating a high-low sensitivity (HLS) pixel circuit, to provide increased dynamic range in an imager. The pixel circuit combines a four transistor (“4T”) and a three-transistor plus capacitor (“3TC”) configuration in one pixel, where the 4T portion of the pixel is coupled to a high sensitivity buried photodiode region, and the 3TC portion of the pixel is coupled to a low sensitivity buried photodiode region. The pixel circuit first reads out charge from the high sensitivity photodiode region and compares it to a reset voltage, then reads out charge from the low sensitivity photodiode region. Under an alternate embodiment, multiple HLS pixels are coupled through a common floating diffusion node.

Abstract: An image sensor chip is formed with the image sensor abutting up to three edges of the chip. Certain parts of the row logic which are required to be adjacent to each of the rows are placed into the array, in place of certain pixels of the array. Those missing pixels are then interpolated.

Abstract: A two-transistor pixel of an imager has a reset region formed adjacent a charge collection region of a photodiode and in electrical communication with a gate of a source follower transistor. The reset region is connected to one terminal of a capacitor which integrates collected charge of the photodiode. The charge collection region is reset by pulsing the other terminal of the capacitor from a higher to a lower voltage.

Abstract: A non-uniform resistor is used with a flash A to D converter in order to provide an A to D output which is not linear. The nonlinearity of the A to D output is specially designed to carry out a predetermined correction of the signal.

Abstract: An imaging device formed as a monolithic complementary metal oxide semiconductor integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node. There is also a readout circuit, part of which can be disposed at the bottom of each column of cells and be common to all the cells in the column. A Simple Floating Gate (SFG) pixel structure could also be employed in the imager to provide a non-destructive readout and smaller pixel sizes.

Abstract: An image fusion is carried out using a look-up table. The look-up table is addressed by the different kinds of images that will be used to carry out the fusion. Each address in the look-up table contains a precomputed image fusion between the two different kinds of images.

Abstract: An image sensor system using offset analog to digital converters. The analog to digital converters require a plurality of clock cycles to carry out the actual conversion. These conversions are offset in time from one another, so that at each clock cycle, new data is available.

Abstract: Automatic exposure adjusting device considers the image on a pixel-by-pixel basis. Each pixel is characterized according to its most significant bits. After the pixels are characterized, the number of pixels in any particular group is counted. That counting is compared with thresholds which set whether the image is over exposed, under exposed, and can optionally also determine if the image is seriously over exposed or seriously under exposed. Adjustment of the exposure is carried out to bring the image to a more desired state.

Abstract: A cascaded imaging storage system for a pixel is disclosed for improving intrascene dynamic range. Charges accumulated in a first capacitor spill over into a second capacitor when a charge storage capacity of the first capacitor is exceeded. A third capacitor may also be provided such that charges accumulated by said second capacitor spill over into the third capacitor when the charge storage capacity of the second capacitor is exceeded.