Patents by Inventor Eric Regan

Eric Regan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11967619
    Abstract: Laterally-gated transistors and lateral Schottky diodes are disclosed. The FET includes a substrate, source and drain electrodes, channel, a gate electrode structure, and a dielectric layer. The gate electrode structure includes an electrode in contact with the channel and a lateral field plate adjacent to the electrode. The dielectric layer is disposed between the lateral field plate and the channel. The lateral field plate contacts the dielectric layer and to modulate an electric field proximal to the gate electrode proximal to the drain or source electrodes. Also disclosed is a gate electrode structure with lateral field plates symmetrically disposed relative to the gate electrode. Also disclosed in a substrate with dielectric structures buried in the substrate remote from the gate electrode structure. A lateral Schottky diode having an anode structure includes an anode (A), cathodes (C) and lateral field plates located between the anode and the cathodes.
    Type: Grant
    Filed: September 16, 2020
    Date of Patent: April 23, 2024
    Assignee: TELEDYNE SCIENTIFIC & IMAGING, LLC
    Inventors: Keisuke Shinohara, Casey King, Eric Regan, Miguel Urteaga
  • Patent number: 11605722
    Abstract: An ohmic contact for a multiple channel FET comprises a plurality of slit-shaped recesses in a wafer on which a multiple channel FET resides, with each recess having a depth at least equal to the depth of the lowermost channel layer. Ohmic metals in and on the sidewalls of each recess provide ohmic contact to each of the multiple channel layers. An ohmic metal-filled linear connecting recess contiguous with the outside edge of each recess may be provided, as well as an ohmic metal contact layer on the top surface of the wafer over and in contact with the ohmic metals in each of the recesses. The present ohmic contact typically serves as a source and/or drain contact for the multiple channel FET. Also described is the use of a regrown material to make ohmic contact with multiple channels, with the regrown material preferably having a corrugated structure.
    Type: Grant
    Filed: May 18, 2020
    Date of Patent: March 14, 2023
    Assignee: Teledyne Scientific & Imaging, LLC
    Inventors: Keisuke Shinohara, Casey King, Eric Regan
  • Publication number: 20220085176
    Abstract: Laterally-gated transistors and lateral Schottky diodes are disclosed. The FET includes a substrate, source and drain electrodes, channel, a gate electrode structure, and a dielectric layer. The gate electrode structure includes an electrode in contact with the channel and a lateral field plate adjacent to the electrode. The dielectric layer is disposed between the lateral field plate and the channel. The lateral field plate contacts the dielectric layer and to modulate an electric field proximal to the gate electrode proximal to the drain or source electrodes. Also disclosed is a gate electrode structure with lateral field plates symmetrically disposed relative to the gate electrode. Also disclosed in a substrate with dielectric structures buried in the substrate remote from the gate electrode structure. A lateral Schottky diode having an anode structure includes an anode (A), cathodes (C) and lateral field plates located between the anode and the cathodes.
    Type: Application
    Filed: September 16, 2020
    Publication date: March 17, 2022
    Inventors: Keisuke Shinohara, Casey King, Eric Regan, Miguel Urteaga
  • Publication number: 20210359097
    Abstract: An ohmic contact for a multiple channel FET comprises a plurality of slit-shaped recesses in a wafer on which a multiple channel FET resides, with each recess having a depth at least equal to the depth of the lowermost channel layer. Ohmic metals in and on the sidewalls of each recess provide ohmic contact to each of the multiple channel layers. An ohmic metal-filled linear connecting recess contiguous with the outside edge of each recess may be provided, as well as an ohmic metal contact layer on the top surface of the wafer over and in contact with the ohmic metals in each of the recesses. The present ohmic contact typically serves as a source and/or drain contact for the multiple channel FET. Also described is the use of a regrown material to make ohmic contact with multiple channels, with the regrown material preferably having a corrugated structure.
    Type: Application
    Filed: May 18, 2020
    Publication date: November 18, 2021
    Inventors: Keisuke Shinohara, Casey King, Eric Regan