Abstract: In an information processing system which has plurality of modules including a processor, a main memory and a plurality of I/O devices, a data transfer switch for performing data transfer operations between the processor, main memory and I/O devices comprises a request bus which has a request bus arbiter for receiving read and write requests from each one of the plurality of modules. A processor memory bus is configured to receive address and data information from a predetermined number of modules, including the processor. The processor memory bus has a data bus arbiter for receiving data read and write requests from each one of the predetermined number of modules which are coupled to the processor memory bus. An internal memory bus is configured to receive address and data information from a predetermined number of modules, including the memory and the I/O devices.

Abstract: A method presents metadata that is used for determining the color correction processes to be performed on image data representing a sequence of moving images (705). Instructions in the metadata controls how many color corrections are to be performed and when such operations occur. The image data is then subjected to the specified color correction operations that are performed at specified times and in a determined order (710). The image data is then rendered as a series of images (715) by a rendering device. Optionally, different regions of the image data may be subjected to different color correction operations.

Abstract: A system for searching a network for network based content related to a search query, such as multimedia and streaming media, includes an adapter for formatting the search query, a first database containing previous search results and a second database for storing currently returnable metadata, a search processor, and at least one search engine kernel comprising a search engine inherent database. The search engine coordinates searching of the first database and the second database, and provides the formatted search query to the search engine kernel. The search processor also provides and receives search results to and from the first database and the second database, and provides search results to the adapter. The system stores a predetermined amount of previous search results in the first database, such that search results for a current search are retrieved from the database, avoiding a search through search engine kernel comprising searchable metadata.

Abstract: In an information processing system which has plurality of modules including a processor, a main memory and a plurality of I/O devices, a data transfer switch for performing data transfer operations between the processor, main memory and I/O devices comprises a request bus which has a request bus arbiter for receiving read and write requests from each one of the plurality of modules. A processor memory bus is configured to receive address and data information from a predetermined number of modules, including the processor. The processor memory bus has a data bus arbiter for receiving data read and write requests from each one of the predetermined number of modules which are coupled to the processor memory bus. An internal memory bus is configured to receive address and data information from a predetermined number of modules, including the memory and the I/O devices.

Abstract: In an information processing system which has plurality of modules including a processor, a main memory and a plurality of I/O devices, a data transfer switch for performing data transfer operations between the processor, main memory and I/O devices comprises a request bus which has a request bus arbiter for receiving read and write requests from each one of the plurality of modules. A processor memory bus is configured to receive address and data information from a predetermined number of modules, including the processor. The processor memory bus has a data bus arbiter for receiving data read and write requests from each one of the predetermined number of modules which are coupled to the processor memory bus. An internal memory bus is configured to receive address and data information from a predetermined number of modules, including the memory and the I/O devices.

Abstract: A method and system for ranking relevancy of metadata associated with media on a computer network, such as multimedia and streaming media, include categorizing the metadata into sets of metadata. The categories are broad categories relating to areas such as who, what, when, and where, such as artist, media type, and creation date, creation location. Weights are assigned to each set of metadata. Weights are related to technical information such as bit rate, duration, sampling rate, frequency of occurrence of a specific term, etc. A score is calculated for ranking the relevancy of each set of metadata. The score is calculated in accordance with the assigned weight and category. This score is available for search systems (e.g., search engines) and/or users to determine the relative ranking of search results.

Abstract: A method and system for utilizing metadata to search for media, such as multimedia and streaming media, includes searching for the media, receiving results, extracting metadata associated with the media, enhancing the extracted metadata, and grouping the search results in accordance with attributes of the enhanced metadata. Enhancing and grouping include adding related metadata to the database of metadata, iteratively using metadata to search for more media related data, removing duplicate URLs, collapsing URLs that are variants of each other, and masking out superfluous terms from URLs. The resultant metadata and media files are available to users and search engines.

Abstract: In an information processing system which has plurality of modules including a processor, a main memory and a plurality of I/O devices, a data transfer switch for performing data transfer operations between the processor, main memory and I/O devices comprises a request bus which has a request bus arbiter for receiving read and write requests from each one of the plurality of modules. A processor memory bus is configured to receive address and data information from a predetermined number of modules, including the processor. The processor memory bus has a data bus arbiter for receiving data read and write requests from each one of the predetermined number of modules which are coupled to the processor memory bus. An internal memory bus is configured to receive address and data information from a predetermined number of modules, including the memory and the I/O devices.