Patents by Inventor Eric Remond

Eric Remond has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Pivotable sheath stop for a sheath, and corresponding bracket, guide rail, assembly, window lift, and mounting method
    Patent number: 9803683
    Abstract: The invention relates to a sheath stop including: a hole through which a window lift cable is to pass; and a sheath abutment for locking the sheath of the window lift cable on one side of the sheath stop and wherein, on the other side of the sheath stop, the sheath stop includes a shaft provided so as to be mounted onto a bracket of the sheath stop such that the sheath stop has a freely rotatable mounting configuration on the bracket. The shaft extends transversely to the main orientation of the passage hole, and the passage hole has a partial side clearance that allows the cable a degree of bending freedom within a plane perpendicular to the shaft when the sheath stop freely pivots about the shaft.
    Type: Grant
    Filed: March 3, 2014
    Date of Patent: October 31, 2017
    Assignee: INTEVA PRODUCTS FRANCE SAS
    Inventors: Eric Simonneau, Nicolas Galliot, Eric Remond, Jean-Louis Robalo
  • Integrated hall effect sensor with a biased buried electrode
    Patent number: 9671473
    Abstract: The generation of a Hall voltage within a semiconductor film of an integrated Hall effect sensor uses the flow of a current within the semiconductor film when subjected to a magnetic field. The film is disposed on top of an insulating layer, referred to as buried layer, which is itself disposed on top of a carrier substrate containing a buried electrode that is situated under the insulating layer. A biasing voltage is applied to the buried electrode.
    Type: Grant
    Filed: May 23, 2014
    Date of Patent: June 6, 2017
    Assignee: STMicroelectronics SA
    Inventors: Severin Trochut, Eric Remond
  • Pivotable Sheath Stop for a Sheath, and Corresponding Bracket, Guide Rail, Assembly, Window Lift, and Mounting Method
    Publication number: 20160047411
    Abstract: The invention relates to a sheath stop including: a hole through which a window lift cable is to pass; and a sheath abutment for locking the sheath of the window lift cable on one side of the sheath stop and wherein, on the other side of the sheath stop, the sheath stop includes a shaft provided so as to be mounted onto a bracket of the sheath stop such that the sheath stop has a freely rotatable mounting configuration on the bracket. The shaft extends transversely to the main orientation of the passage hole, and the passage hole has a partial side clearance that allows the cable a degree of bending freedom within a plane perpendicular to the shaft when the sheath stop freely pivots about the shaft.
    Type: Application
    Filed: March 3, 2014
    Publication date: February 18, 2016
    Inventors: Eric Simonneau, Nicolas Galliot, Eric Remond, Jean-Louis Robalo
  • Device with FD-SOI cell and insulated semiconductor contact region and related methods
    Patent number: 9147695
    Abstract: An integrated cell may include an nMOS transistor, and an pMOS transistor. The cell may be produced in fully depleted silicon-on-insulator technology, and it is possible for the substrates of the transistors of the cell to be biased with the same adjustable biasing voltage.
    Type: Grant
    Filed: December 4, 2013
    Date of Patent: September 29, 2015
    Assignee: STMICROELECTRONICS SA
    Inventors: Frédéric Hasbani, Eric Remond
  • INTEGRATED HALL EFFECT SENSOR
    Publication number: 20140354276
    Abstract: The generation of a Hall voltage within a semiconductor film of an integrated Hall effect sensor uses the flow of a current within the semiconductor film when subjected to a magnetic field. The film is disposed on top of an insulating layer, referred to as buried layer, which is itself disposed on top of a carrier substrate containing a buried electrode that is situated under the insulating layer. A biasing voltage is applied to the buried electrode.
    Type: Application
    Filed: May 23, 2014
    Publication date: December 4, 2014
    Applicant: STMicroelectronics SA
    Inventors: Severin Trochut, Eric Remond
  • CMOS CELL PRODUCED IN FD-SOI TECHNOLOGY
    Publication number: 20140167167
    Abstract: An integrated cell may include an nMOS transistor, and an pMOS transistor. The cell may be produced in fully depleted silicon-on-insulator technology, and it is possible for the substrates of the transistors of the cell to be biased with the same adjustable biasing voltage.
    Type: Application
    Filed: December 4, 2013
    Publication date: June 19, 2014
    Applicant: STMICROELECTRONICS SA
    Inventors: Frederic HASBANI, Eric Remond