Patents by Inventor Eric Rentschler
Eric Rentschler has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9686536Abstract: A video device having data lanes and a method of operating the video device includes generating performance monitoring and/or debug data in response to the operation of the video device. The generated data is sampled from component of the video device operating in various clocking domain. The data sampled from the components is combined into a unified stream which is independent of the various clocking domain. The unified stream is transmitted across one more data lanes of a video link along with corresponding audio and/or video data in real time.Type: GrantFiled: May 20, 2014Date of Patent: June 20, 2017Assignee: Advanced Micro Devices, Inc.Inventors: Eric Rentschler, Sebastien Nussbaum
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Patent number: 9329963Abstract: Methods and apparatus are provided that facilitate debugging operations for components that may include different power domains. In an embodiment, an integrated circuit (IC) includes a plurality of hardware sectors, each hardware sector associated with a debug observability circuit that is served by a debug data bus of a debug circuit. The plurality of hardware sectors includes a controlled sector residing in a dynamically-controlled power domain that may be turned off while the power domain of another sector remains on. A selectively switchable data bus component is configured to couple the debug observability circuit associated with the controlled sector to the debug data bus when the power to the controlled sector is on and to switch to bypass the debug observability circuit associated with the controlled sector when the power to the controlled sector is not on.Type: GrantFiled: September 16, 2013Date of Patent: May 3, 2016Assignee: Advanced Micro Devices, Inc.Inventors: Shantanu K. Sarangi, Christian Warling, Eric Rentschler, Vikram Chopra, Mihir Doctor
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Patent number: 9262293Abstract: Methods and apparatus are provided that facilitate debugging operations for components in dynamic power domains. In an embodiment, an integrated circuit includes hardware sectors associated with observability circuits served by a debug data bus of a debug circuit. A controlled sector residing in a dynamically-controlled power domain may be turned off while the power domain of another sector remains on. To continue to have debug observability all the way through and after these power events, a debug data register is configured to provide data, such as configuration and/or programming data, to the observability circuit of the controlled sector via the debug data bus. A shadow register is configured to capture the data provided to the controlled sector's observability circuit. The shadow register data is used upon restoring power to the controlled sector to restore the controlled sector's observability circuit to a state when the controlled sector was previously powered on.Type: GrantFiled: September 16, 2013Date of Patent: February 16, 2016Assignee: Advanced Micro Devices, Inc.Inventors: Shantanu K. Sarangi, Eric Rentschler, Rahul Dev, Vikram Chopra, Mihir Doctor
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Publication number: 20150082092Abstract: Methods and apparatus are provided that facilitate debugging operations for components that may include different power domains. In an embodiment, an integrated circuit (IC) includes a plurality of hardware sectors, each hardware sector associated with a debug observability circuit that is served by a debug data bus of a debug circuit. The plurality of hardware sectors includes a controlled sector residing in a dynamically-controlled power domain that may be turned off while the power domain of another sector remains on. A selectively switchable data bus component is configured to couple the debug observability circuit associated with the controlled sector to the debug data bus when the power to the controlled sector is on and to switch to bypass the debug observability circuit associated with the controlled sector when the power to the controlled sector is not on.Type: ApplicationFiled: September 16, 2013Publication date: March 19, 2015Applicant: Advanced Micro Devices, Inc.Inventors: Shantanu K. Sarangi, Christian Warling, Eric Rentschler, Vikram Chopra, Mihir Doctor
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Publication number: 20150082093Abstract: Methods and apparatus are provided that facilitate debugging operations for components in dynamic power domains. In an embodiment, an integrated circuit includes hardware sectors associated with observability circuits served by a debug data bus of a debug circuit. A controlled sector residing in a dynamically-controlled power domain may be turned off while the power domain of another sector remains on. To continue to have debug observability all the way through and after these power events, a debug data register is configured to provide data, such as configuration and/or programming data, to the observability circuit of the controlled sector via the debug data bus. A shadow register is configured to capture the data provided to the controlled sector's observability circuit. The shadow register data is used upon restoring power to the controlled sector to restore the controlled sector's observability circuit to a state when the controlled sector was previously powered on.Type: ApplicationFiled: September 16, 2013Publication date: March 19, 2015Applicant: Advanced Micro Devices, Inc.Inventors: Shantanu K. Sarangi, Eric Rentschler, Rahul Dev, Vikram Chopra, Mihir Doctro
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Patent number: 8595563Abstract: Described are a circuit and a method of analyzing and correcting a fault occurring in operation of the circuit during a power gating sequence. The method includes executing a modification of the power gating sequence that includes maintaining operation of a trace capture buffer (TCB); recording, in the TCB, events occurring during the executing; and correcting the fault based on analysis of the events recorded in the TCB. The circuit includes a plurality of components including a TCB, and a switch configured to maintain power to the TCB in a first state and turn off power to the TCB in a second state.Type: GrantFiled: July 18, 2011Date of Patent: November 26, 2013Assignee: Advanced Micro Devices, Inc.Inventors: Benjamin Tsien, Kiran Bondalapati, Hao Huang, William A. Hughes, Eric Rentschler, Jeremy Schreiber, Aaron J. Grenat
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Patent number: 8566645Abstract: A processor or an integrated circuit chip including a debug state machine (DSM) that allows for programming complex triggering sequences for flexible and efficient debug visibility is disclosed. The DSM centralizes control of local debug functions such as trace start and stop, trace filtering, cross triggering between DSMs, clock stopping, triggering a system debug mode interrupt, flexible microcode interface, and the like. The DSM is configured to receive triggers from a processor core, other DSMs, a northbridge, other sockets, and the like and initiate a programmed action on a condition that a corresponding trigger or a sequence of triggers occurs.Type: GrantFiled: December 2, 2010Date of Patent: October 22, 2013Assignee: Advanced Micro Devices, Inc.Inventors: Eric Rentschler, Steven J. Kommrusch, Scott P. Nixon
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Publication number: 20130024829Abstract: Described are a circuit and a method of analyzing and correcting a fault occurring in operation of the circuit during a power gating sequence. The method includes executing a modification of the power gating sequence that includes maintaining operation of a trace capture buffer (TCB); recording, in the TCB, events occurring during the executing; and correcting the fault based on analysis of the events recorded in the TCB. The circuit includes a plurality of components including a TCB, and a switch configured to maintain power to the TCB in a first state and turn off power to the TCB in a second state.Type: ApplicationFiled: July 18, 2011Publication date: January 24, 2013Applicant: ADVANCED MICRO DEVICES, INC.Inventors: Benjamin Tsien, Kiran Bondalapati, Hao Huang, William A. Hughes, Eric Rentschler, Jeremy Schreiber, Aaron J. Grenat
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Publication number: 20120144240Abstract: A processor or an integrated circuit chip including a debug state machine (DSM) that allows for programming complex triggering sequences for flexible and efficient debug visibility is disclosed. The DSM centralizes control of local debug functions such as trace start and stop, trace filtering, cross triggering between DSMs, clock stopping, triggering a system debug mode interrupt, flexible microcode interface, and the like. The DSM is configured to receive triggers from a processor core, other DSMs, a northbridge, other sockets, and the like and initiate a programmed action on a condition that a corresponding trigger or a sequence of triggers occurs.Type: ApplicationFiled: December 2, 2010Publication date: June 7, 2012Applicant: ADVANCED MICRO DEVICES, INC.Inventors: Eric Rentschler, Steven J. Kommrusch, Scott P. Nixon
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Publication number: 20050238127Abstract: Systems, methods, and other embodiments associated with synchronizing link delay is provided. In one example system, a system for synchronizing signal communication between a first electronic component and a second electronic component connected by one or more serial communication links comprises an offset logic configured to apply a selected offset to signal transmissions to cause a unidirectional delay between the first and the second electronic components to be synchronized for both directions of signal transmissions. A synchronization logic is configured to determine the uni-directional delay for signal transmissions between the first and second electronic components and configured to control the offset logic to apply the selected offset.Type: ApplicationFiled: April 22, 2004Publication date: October 27, 2005Inventors: Samuel Naffziger, Eric Rentschler
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Publication number: 20050240698Abstract: Systems, methods, and other embodiments associated with a repeatable communication system are disclosed. One example system for receiving signals from an electronic component over a plurality of point-to-point communication links comprises a repeatability logic operably connected to each of the plurality of point-to-point communication links and configured to apply a delay offset to the signals received to compensate for frequency changes in signal transmissions over the plurality of point-to-point communication links.Type: ApplicationFiled: April 22, 2004Publication date: October 27, 2005Inventors: Eric Rentschler, Samuel Naffziger
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Publication number: 20050071554Abstract: Embodiments of the present invention are broadly directed to a memory system. In one embodiment, a first data memory is coupled to a first memory controller and a second data memory is coupled to a second memory controller. A parity memory is coupled to a parity controller, the parity controller being directly coupled to both the first memory controller and the second memory controller. Parity data control logic is configured to store and retrieve parity information associated with data stored in both the first data memory and the second data memory, the parity data control logic configured to interleave within the parity memory parity data associated with data stored in the first data memory with parity data associated with data stored in the second data memory.Type: ApplicationFiled: September 29, 2003Publication date: March 31, 2005Inventors: Larry Thayer, Eric Rentschler, Michael Tayler
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Publication number: 20050047222Abstract: A clock signal aligned relative to an edge of a strobe signal received from a transmitting device is generated. One or more data signals received from the transmitting device are latched using the clock signal.Type: ApplicationFiled: August 27, 2003Publication date: March 3, 2005Inventor: Eric Rentschler
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Publication number: 20050028069Abstract: The present invention is broadly directed to a memory system comprising a a host integrated circuit component, at least two data memories, at least one parity memory for storing parity information corresponding to data stored in a corresponding address space of the data memories, and at least two controller integrated circuits. Each controller integrated circuit (IC) comprises memory control logic configurable to control communications between the controller IC and data memories directly connected to the controller IC, parity logic configurable to compute parity information for data communicated to or from the data memories, logic configurable to communicate the parity information to or from a companion IC, and logic configurable to communicated data to or from a companion IC.Type: ApplicationFiled: July 31, 2003Publication date: February 3, 2005Inventors: Larry Thayer, Eric Rentschler, Michael Tayler
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Publication number: 20050027891Abstract: The present invention is broadly directed to a integrated circuit component with a scalable architecture. In one embodiment, an integrated circuit component is provided comprising logic capable of being configured to interface with a first portion of a system bus, and logic capable of being configured to interface with a companion integrated circuit and to receive information that is communicated from the companion integrated circuit, which information was communicated to the companion integrated circuit via a second portion of the system bus.Type: ApplicationFiled: July 30, 2003Publication date: February 3, 2005Inventors: Darel Emmot, Eric Rentschler, Michael Tayler
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Patent number: 5940086Abstract: A system and associated method for dynamically allocating vertex data to a plurality of geometry accelerators in a computer graphics system based upon the relative current capability of the geometry accelerators to process the data. This efficient distribution of vertex data substantially reduces the amount of time individual geometry accelerators remain idle, thereby increasing both the efficiency of each geometry accelerator as well as the overall parallel processing of vertex data. This selective utilization of geometry accelerators thereby results in a significant increase in the throughput performance of the computer graphics system. A computer graphics system in accordance with the present invention comprises a plurality of geometry accelerators and a distributor connected through two unidirectional buses that transmit data in opposite directions. The geometry accelerators are connected, through appropriate interfacing hardware, directly to an input bus.Type: GrantFiled: January 10, 1997Date of Patent: August 17, 1999Assignee: Hewlett Packard CompanyInventors: Eric Rentschler, Alan S. Krech, Jr., Noel D. Scott
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Patent number: 5920326Abstract: A computer graphics system for rendering graphics primitives based upon primitive data received from a host computer through a graphics interface. The primitive data may include vertex state and property state values. The computer graphics system includes a plurality of geometry accelerators configured to process the primitive data to render graphics primitives. The graphics primitives are rendered from one or more vertex states in accordance with the property states currently maintained in the rendering geometry accelerator. A distributor divides the primitive data into chunks of primitive data and distributes each of the primitive data chunks to a current geometry accelerator recipient. In one aspect of the invention, the distributor includes a state controller interposed between the host computer and said plurality of geometry accelerators.Type: GrantFiled: May 30, 1997Date of Patent: July 6, 1999Assignee: Hewlett Packard CompanyInventors: Eric Rentschler, Alan S. Krech, Jr., Kendall F Tidwell