Patents by Inventor Eric Russell Peterson

Eric Russell Peterson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7362702
    Abstract: A router for use in a network includes a scalable architecture and performs methods for implementing quality of service on a logical unit behind a network port; and for implementing storage virtualization. The architecture includes a managing processor, a supervising processor; and a plurality of routing processors coupled to a fabric. The managing processor has an in-band link to a routing processor. A routing processor receives a frame from the network, determines by parsing the frame, the protocol and logical unit number, and routes the frame to a queue according to a traffic class associated with the logical unit number in routing information prepared for the processors. An arbitration scheme empties the queue in accordance with a deficit round robin technique. If a routing processor detects the frame's destination is a virtual entity, and so is part of a virtual transaction, the router conducts a nonvirtual transaction in concert with the virtual transaction.
    Type: Grant
    Filed: October 29, 2002
    Date of Patent: April 22, 2008
    Assignee: QLOGIC, Corporation
    Inventors: William C. Terrell, Tracy Edmonds, Wayland Joeng, Eric Russell Peterson, Jean Kodama, Harun Muliadi, Norman Chan, Rexford Hill, Michael Nishimura, Stephen How
  • Patent number: 7292567
    Abstract: A router for use in a network includes a scalable architecture and performs methods for implementing quality of service on a logical unit behind a network port; and for implementing storage virtualization. The architecture includes a managing processor, a supervising processor; and a plurality of routing processors coupled to a fabric. The managing processor has an in-band link to a routing processor. A routing processor receives a frame from the network, determines by parsing the frame, the protocol and logical unit number, and routes the frame to a queue according to a traffic class associated with the logical unit number in routing information prepared for the processors. An arbitration scheme empties the queue in accordance with a deficit round robin technique. If a routing processor detects the frame's destination is a virtual entity, and so is part of a virtual transaction, the router conducts a nonvirtual transaction in concert with the virtual transaction.
    Type: Grant
    Filed: October 31, 2002
    Date of Patent: November 6, 2007
    Assignee: QLogic Corporation
    Inventors: William C. Terrell, Tracy Edmonds, Wayland Joeng, Eric Russell Peterson, Jean Kodama, Harun Muliadi, Norman Chan, Rexford Hill, Michael Nishimura, Stephen How
  • Patent number: 7200144
    Abstract: A router for use in a network includes a scalable architecture and performs methods for implementing quality of service on a logical unit behind a network port; and for implementing storage virtualization. The architecture includes a managing processor, a supervising processor; and a plurality of routing processors coupled to a fabric. The managing processor has an in-band link to a routing processor. A routing processor receives a frame from the network, determines by parsing the frame, the protocol and logical unit number, and routes the frame to a queue according to a traffic class associated with the logical unit number in routing information prepared for the processors. An arbitration scheme empties the queue in accordance with a deficit round robin technique. If a routing processor detects the frame's destination is a virtual entity, and so is part of a virtual transaction, the router conducts a nonvirtual transaction in concert with the virtual transaction.
    Type: Grant
    Filed: October 18, 2001
    Date of Patent: April 3, 2007
    Assignee: Qlogic, Corp.
    Inventors: William C. Terrell, Tracy Edmonds, Wayland Joeng, Eric Russell Peterson, Jean Kodama, Harun Muliadi, Norman Chan, Rexford Hill, Michael Nishimura, Stephen How
  • Publication number: 20030189930
    Abstract: A router for use in a network includes a scalable architecture and performs methods for implementing quality of service on a logical unit behind a network port; and for implementing storage virtualization. The architecture includes a managing processor, a supervising processor; and a plurality of routing processors coupled to a fabric. The managing processor has an in-band link to a routing processor. A routing processor receives a frame from the network, determines by parsing the frame, the protocol and logical unit number, and routes the frame to a queue according to a traffic class associated with the logical unit number in routing information prepared for the processors. An arbitration scheme empties the queue in accordance with a deficit round robin technique. If a routing processor detects the frame's destination is a virtual entity, and so is part of a virtual transaction, the router conducts a nonvirtual transaction in concert with the virtual transaction.
    Type: Application
    Filed: October 29, 2002
    Publication date: October 9, 2003
    Inventors: William C. Terrell, Tracy Edmonds, Wayland Jeong, Eric Russell Peterson, Jean Kodama, Harun Muliadi, Norman Chan, Rexford Hill, Michael Nishimura, Stephen How
  • Publication number: 20030189936
    Abstract: A router for use in a network includes a scalable architecture and performs methods for implementing quality of service on a logical unit behind a network port; and for implementing storage virtualization. The architecture includes a managing processor, a supervising processor; and a plurality of routing processors coupled to a fabric. The managing processor has an in-band link to a routing processor. A routing processor receives a frame from the network, determines by parsing the frame, the protocol and logical unit number, and routes the frame to a queue according to a traffic class associated with the logical unit number in routing information prepared for the processors. An arbitration scheme empties the queue in accordance with a deficit round robin technique. If a routing processor detects the frame's destination is a virtual entity, and so is part of a virtual transaction, the router conducts a nonvirtual transaction in concert with the virtual transaction.
    Type: Application
    Filed: October 31, 2002
    Publication date: October 9, 2003
    Inventors: William C. Terrell, Tracy Edmonds, Wayland Jeong, Eric Russell Peterson, Jean Kodama, Harun Muliadi, Norman Chan, Rexford Hill, Michael Nishimura, Stephen How
  • Publication number: 20030191857
    Abstract: A router for use in a network includes a scalable architecture and performs methods for implementing quality of service on a logical unit behind a network port; and for implementing storage virtualization. The architecture includes a managing processor, a supervising processor; and a plurality of routing processors coupled to a fabric. The managing processor has an in-band link to a routing processor. A routing processor receives a frame from the network, determines by parsing the frame, the protocol and logical unit number, and routes the frame to a queue according to a traffic class associated with the logical unit number in routing information prepared for the processors. An arbitration scheme empties the queue in accordance with a deficit round robin technique. If a routing processor detects the frame's destination is a virtual entity, and so is part of a virtual transaction, the router conducts a nonvirtual transaction in concert with the virtual transaction.
    Type: Application
    Filed: October 30, 2002
    Publication date: October 9, 2003
    Inventors: William C. Terrell, Tracy Edmonds, Wayland Jeong, Eric Russell Peterson, Jean Kodama, Harun Muliadi, Norman Chan, Rexford Hill, Michael Nishimura, Stephen How