Abstract: Some embodiments include apparatuses and methods forming the apparatuses. One of the apparatuses includes a first transistor including a first channel region, and a charge storage structure separated from the first channel region; a second transistor including a second channel region formed over the charge storage structure; and a data line formed over and contacting the first channel region and the second channel region, the data line including a portion adjacent the first channel region and separated from the first channel region by a dielectric material.

Abstract: Some embodiments include apparatuses and methods of operating such apparatuses. One of such apparatuses includes a data line, a conductive region, and a memory cell including a first transistor and a second transistor. The first transistor includes a first channel region coupled to the data line and the conductive region, a charge storage structure, and a first gate. The second transistor includes a second channel region coupled to the data line and the charge storage structure, and a second gate. The first gate is electrically separated from the second gate and opposite from the second gate in a direction from the first channel region to the second channel region.

Abstract: Methods, systems, and devices for self-refresh of memory cells are described. A controller coupled with a memory cell may be configured to apply a first voltage to a control gate of a first transistor, where the first voltage activates the first transistor to selectively couple terminals of the first transistor with each other based on a charge stored on the interstitial gate. The controller may be configured to apply a current to a bit line, where a second voltage of the bit line is based on the current and the charge stored on the interstitial gate. The controller may be configured to apply, based on applying the first voltage to the control gate of the first transistor and applying the current to the bit line, a third voltage to a gate of a second transistor to couple the bit line with the interstitial gate of the first transistor.

Abstract: Methods, a memory device, and a system are disclosed to reduce power consumption in a cross-point memory device, including providing a first portion of a first pulse of a memory operation to a memory cell at a first time using a first capacitive discharge from a first discharge path, and providing a second portion of the first pulse of the memory operation to the memory cell at a second time, later than the first time, using a second discharge path.

Abstract: Some embodiments include apparatuses and methods of operating such apparatuses. One of such apparatuses includes a data line, a conductive region, and a memory cell including a first transistor and a second transistor. The first transistor includes a first channel region coupled to the data line and the conductive region, a charge storage structure, and a first gate. The second transistor includes a second channel region coupled to the data line and the charge storage structure, and a second gate. The first gate is electrically separated from the second gate and opposite from the second gate in a direction from the first channel region to the second channel region.

Abstract: Some embodiments include apparatuses and methods forming the apparatuses. One of the apparatuses includes a first transistor including a first channel region, and a charge storage structure separated from the first channel region; a second transistor including a second channel region formed over the charge storage structure; and a data line formed over and contacting the first channel region and the second channel region, the data line including a portion adjacent the first channel region and separated from the first channel region by a dielectric material.

Abstract: Some embodiments include apparatuses and methods forming the apparatuses. One of the apparatuses includes a first transistor including a first channel region, and a charge storage structure separated from the first channel region; a second transistor including a second channel region formed over the charge storage structure; and a data line formed over and contacting the first channel region and the second channel region, the data line including a portion adjacent the first channel region and separated from the first channel region by a dielectric material.

Abstract: Methods, systems, and devices for self-refresh of memory cells are described. A controller coupled with a memory cell may be configured to apply a first voltage to a control gate of a first transistor, where the first voltage activates the first transistor to selectively couple terminals of the first transistor with each other based on a charge stored on the interstitial gate. The controller may be configured to apply a current to a bit line, where a second voltage of the bit line is based on the current and the charge stored on the interstitial gate. The controller may be configured to apply, based on applying the first voltage to the control gate of the first transistor and applying the current to the bit line, a third voltage to a gate of a second transistor to couple the bit line with the interstitial gate of the first transistor.

Abstract: Some embodiments include apparatuses and methods of operating such apparatuses. One of such apparatuses includes a data line, a conductive region, and a memory cell including a first transistor and a second transistor. The first transistor includes a first channel region coupled to the data line and the conductive region, a charge storage structure, and a first gate. The second transistor includes a second channel region coupled to the data line and the charge storage structure, and a second gate. The first gate is electrically separated from the second gate and opposite from the second gate in a direction from the first channel region to the second channel region.

Abstract: Methods, systems, and devices for self-refresh of memory cells are described. A controller coupled with a memory cell may be configured to apply a first voltage to a control gate of a first transistor, where the first voltage activates the first transistor to selectively couple terminals of the first transistor with each other based on a charge stored on the interstitial gate. The controller may be configured to apply a current to a bit line, where a second voltage of the bit line is based on the current and the charge stored on the interstitial gate. The controller may be configured to apply, based on applying the first voltage to the control gate of the first transistor and applying the current to the bit line, a third voltage to a gate of a second transistor to couple the bit line with the interstitial gate of the first transistor.

Abstract: Methods, systems, and devices for self-refresh of memory cells are described. A controller coupled with a memory cell may be configured to apply a first voltage to a control gate of a first transistor, where the first voltage activates the first transistor to selectively couple terminals of the first transistor with each other based on a charge stored on the interstitial gate. The controller may be configured to apply a current to a bit line, where a second voltage of the bit line is based on the current and the charge stored on the interstitial gate. The controller may be configured to apply, based on applying the first voltage to the control gate of the first transistor and applying the current to the bit line, a third voltage to a gate of a second transistor to couple the bit line with the interstitial gate of the first transistor.

Abstract: Methods, systems, techniques, and devices for operating a ferroelectric memory cell or cells are described. A first ferroelectric memory cell may be used to charge a second ferroelectric memory cell by transferring charge from a plate of first ferroelectric memory cell to a plate of the second ferroelectric memory cell. In some examples, prior to the transfer of charge, the first ferroelectric memory cell may be selected for a first operation in which the first ferroelectric memory cell transitions from a charged state to a discharged state and the second ferroelectric memory cell may be selected for a second operation during which the second ferroelectric memory cell transitions from a discharged state to a charged state. The discharging of the first ferroelectric memory cell may be used to assist in charging the second ferroelectric memory cell.

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A ground reference scheme may be employed in a digit line voltage sensing operation. A positive voltage may be applied to a memory cell; and after a voltage of the digit line of the cell has reached a threshold, a negative voltage may be applied to cause the digit line voltages to center around ground before a read operation. In another example, a first voltage may be applied to a memory cell and then a second voltage that is equal to an inverse of the first voltage may be applied to a reference capacitor that is in electronic communication with a digit line of the memory cell to cause the digit line voltages to center around ground before a read operation.

Abstract: Methods, a memory device, and a system are disclosed to reduce power consumption in a cross-point memory device, including providing a first portion of a first pulse of a memory operation to a memory cell at a first time using a first capacitive discharge from a first discharge path, and providing a second portion of the first pulse of the memory operation to the memory cell at a second time, later than the first time, using a second discharge path.

Abstract: Methods, systems, techniques, and devices for operating a ferroelectric memory cell or cells are described. A first ferroelectric memory cell may be used to charge a second ferroelectric memory cell by transferring charge from a plate of first ferroelectric memory cell to a plate of the second ferroelectric memory cell. In some examples, prior to the transfer of charge, the first ferroelectric memory cell may be selected for a first operation in which the first ferroelectric memory cell transitions from a charged state to a discharged state and the second ferroelectric memory cell may be selected for a second operation during which the second ferroelectric memory cell transitions from a discharged state to a charged state. The discharging of the first ferroelectric memory cell may be used to assist in charging the second ferroelectric memory cell.

Abstract: Methods, a memory device, and a system are disclosed. One such method includes providing a first pulse to one of multiple bit lines of a variable resistance memory structure at a first time using a first transistor, a second pulse to the one of the multiple bit lines at a second time later than the first time using the first transistor, and a third pulse to the one of the multiple bit lines at a third time later than the second time using a second transistor.

Abstract: Methods, systems, techniques, and devices for operating a ferroelectric memory cell or cells are described. A first ferroelectric memory cell may be used to charge a second ferroelectric memory cell by transferring charge from a plate of first ferroelectric memory cell to a plate of the second ferroelectric memory cell. In some examples, prior to the transfer of charge, the first ferroelectric memory cell may be selected for a first operation in which the first ferroelectric memory cell transitions from a charged state to a discharged state and the second ferroelectric memory cell may be selected for a second operation during which the second ferroelectric memory cell transitions from a discharged state to a charged state. The discharging of the first ferroelectric memory cell may be used to assist in charging the second ferroelectric memory cell.

Abstract: Methods, systems, techniques, and devices for operating a ferroelectric memory cell or cells are described. A first ferroelectric memory cell may be used to charge a second ferroelectric memory cell by transferring charge from a plate of first ferroelectric memory cell to a plate of the second ferroelectric memory cell. In some examples, prior to the transfer of charge, the first ferroelectric memory cell may be selected for a first operation in which the first ferroelectric memory cell transitions from a charged state to a discharged state and the second ferroelectric memory cell may be selected for a second operation during which the second ferroelectric memory cell transitions from a discharged state to a charged state. The discharging of the first ferroelectric memory cell may be used to assist in charging the second ferroelectric memory cell.

Abstract: Methods, a memory device, and a system are disclosed. One such method includes providing a first pulse to one of multiple bit lines of a variable resistance memory structure at a first time using a first transistor, a second pulse to the one of the multiple bit lines at a second time later than the first time using the first transistor, and a third pulse to the one of the multiple bit lines at a third time later than the second time using a second transistor.

Abstract: Methods, a memory device, and a system are disclosed. One such method includes applying a select pulse to a snapback device of a memory cell. This causes the memory cell to enter a conductive state. Once in the conductive state, the memory cell can be set or reset by a pulse formed from parasitic capacitive discharge from various paths coupled to the memory cell.