Abstract: A system for reducing the number of I/O requests required to write data to an redundant array of inexpensive disks (RAID) of a computer system including a host central processor unit and a memory buffer cache. The system includes determinations for writing new data stored in the cache to the disk drives, as stripes, using the least number of I/O requests possible. The system uses the best of two alternative techniques in which the parity for the stripe can be generated. A first procedure determines the number of I/O requests that would be required to generate the parity data from the entire stripe including the new data to be written to the disk drives. A second procedure determines the number of I/O requests that would be required to generate the parity data from the new data to be written to the disk drives and the old parity data of the stripe.

Abstract: A method for prefetching the data and parity blocks for generating parity data of a stripe. The method uses a low and high thresholds marker indicative of a first and second level of fullness of the cache to determine whether or not to prefetch the data and parity blocks. If the cache is filled to a level exceeding the first level of fullness, the data and parity blocks are prefetched for any blocks to be written to the disk drive between the low and high threshold. The data and parity blocks are read from the disk drive at a lower processing priority in anticipation of the writing of the block.

Abstract: A method and apparatus for a software actuable backup power controller for selectively controlling power to a volatile random access cache memory. If memory does not contain any data that needs to be retained during a primary power failure the controller isolates memory from the backup power supply during the power failure. Only when the memory contains data to be retained during a power failure will memory be treated as non-volatile and is the backup power supply connected to memory on primary power failure. By selectively enabling the backup power supply with software commands from the computer, a suitable cache memory can be constructed with a compact non-rechargeable battery.