Patents by Inventor Eric S. Tosaya

Eric S. Tosaya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9524883
    Abstract: A workpiece (120) has protruding conductive features (140) at least on a first side. The second side is processed while the workpiece is held from the first side by a holder (220H). To prevent damage to the protruding features and flatten the workpiece (which could be otherwise warped), a spacer (210) is inserted between the workpiece and the holder. The spacer has holes (250) receiving the protruding features. The workpiece can be held by forces generated by the holder such as vacuum or an electrostatic force, without an adhesive. Other features and advantages are provided.
    Type: Grant
    Filed: November 6, 2014
    Date of Patent: December 20, 2016
    Assignee: Invensas Corporation
    Inventors: Charles G. Woychik, Eric S. Tosaya, Rajesh Katkar
  • Patent number: 9496154
    Abstract: A microelectronic component (110, 120) has a contact pad (110C, 120C, 920C) recessed in a cavity (410) and covered by underfill tape (130). The cavity has a void (410V) below the underfill tape. A protruding contact pad of another microelectronic component ruptures the underfill tape to enter the cavity and bond to the recessed contact pad. The void helps in rupturing the underfill tape, thus reducing the amount of underfill residue between the two contact pads and improving the contact resistance. Also provided is a microelectronic component having a substrate with a cavity and having a through-substrate via extending into the cavity. Other features are also provided.
    Type: Grant
    Filed: September 16, 2014
    Date of Patent: November 15, 2016
    Assignee: Invensas Corporation
    Inventors: Eric S. Tosaya, Rajesh Katkar, Liang Wang, Cyprian Emeka Uzoh
  • Publication number: 20160079093
    Abstract: A microelectronic component (110, 120) has a contact pad (110C, 120C, 920C) recessed in a cavity (410) and covered by underfill tape (130). The cavity has a void (410V) below the underfill tape. A protruding contact pad of another microelectronic component ruptures the underfill tape to enter the cavity and bond to the recessed contact pad. The void helps in rupturing the underfill tape, thus reducing the amount of underfill residue between the two contact pads and improving the contact resistance. Also provided is a microelectronic component having a substrate with a cavity and having a through-substrate via extending into the cavity. Other features are also provided.
    Type: Application
    Filed: September 16, 2014
    Publication date: March 17, 2016
    Inventors: Eric S. TOSAYA, Rajesh KATKAR, Liang WANG, Cyprian Emeka UZOH
  • Publication number: 20150333049
    Abstract: A workpiece (120) has protruding conductive features (140) at least on a first side. The second side is processed while the workpiece is held from the first side by a holder (220H). To prevent damage to the protruding features and flatten the workpiece (which could be otherwise warped), a spacer (210) is inserted between the workpiece and the holder. The spacer has holes (250) receiving the protruding features. The workpiece can be held by forces generated by the holder such as vacuum or an electrostatic force, without an adhesive. Other features and advantages are provided.
    Type: Application
    Filed: November 6, 2014
    Publication date: November 19, 2015
    Inventors: Charles G. Woychik, Eric S. Tosaya, Rajesh Katkar
  • Publication number: 20130258619
    Abstract: Various circuit boards and stiffener frames and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes fabricating a stiffener frame that has a surface adapted to engage a side of a circuit board. The surface includes a projection to protect a corner of the circuit board.
    Type: Application
    Filed: March 30, 2012
    Publication date: October 3, 2013
    Inventors: Tom J. Ley, Eric S. Tosaya, Chia-Ken Leong
  • Patent number: 6538320
    Abstract: A heat spreader-package assembly is provided having a heat spreader mounted to a package board with an adhesive. The heat spreader has an upper portion and a plurality of sidewalls extending from the upper portion. The heat spreader has a flange that extends from the sidewalls continuously about a periphery of the upper portion and has a plurality of holes. The holes allow the uncured adhesive to flow therethrough. When the adhesive has cured, a head is formed from the adhesive on an upper side of the flange to establish a riveted connection.
    Type: Grant
    Filed: June 28, 2001
    Date of Patent: March 25, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Eric S. Tosaya, Edward S. Alcid
  • Patent number: 6512675
    Abstract: An intregrated circuit package, which has an intregrated circuit die thereto, is mounted to a system board. The ground trace of the system board is connected to the package, which has a pluality of ground leads on its surface. An electrically conductive epoxy is placed on the ground leads and adheres the package lid to the package board and ground the package lid. A heat sink is mounted to the package lid with an electrically conductive adhesive or electrically conductive slips that extend from a flange of the package lid to a flange of the heat sink to ground the heat sink.
    Type: Grant
    Filed: January 19, 2001
    Date of Patent: January 28, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Thomas S. Tarter, Eric S. Tosaya, Tom J. Ley, Shrikar Bhagath, Nhon T. Do
  • Patent number: 6508845
    Abstract: A method and apparatus for precoining a ball grid array (BGA) type package prior to electrical characterization of the package employs a heated pressing plate with a smooth, flat bottom. The heated pressing plate is controllably pressed against a plurality of solder balls attached to a chip scale package. The heated pressing planarizes the tops of the solder balls, thereby evening out height differences among the solder balls. With the height differences evened out, a grounding plate of a test fixture can be applied on the array of solder balls and reliably contact each of the solder balls that are to be grounded, regardless of their initial height differences.
    Type: Grant
    Filed: May 22, 2002
    Date of Patent: January 21, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Eric S. Tosaya
  • Patent number: 6483169
    Abstract: An extruded heat exchanger that reduces manufacturing costs and material waste, without compromising heat spreading effects. The heat exchanger has an upper surface that is thermally coupled to a heat sink. Two sidewalls extend only from opposite edges of the upper surface. A flange extends from each of the opposing sidewalls.
    Type: Grant
    Filed: June 28, 2001
    Date of Patent: November 19, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Eric S. Tosaya, Edward S. Alcid
  • Patent number: 6399474
    Abstract: A method and apparatus for precoining a ball grid array (BGA) type package prior to electrical characterization of the package employs a heated pressing plate with a smooth, flat bottom. The heated pressing plate is controllably pressed against a plurality of solder balls attached to a chip scale package. The heated pressing planarizes the tops of the solder balls, thereby evening out height differences among the solder balls. With the height differences evened out, a grounding plate of a test fixture can be applied on the array of solder balls and reliably contact each of the solder balls that are to be grounded, regardless of their initial height differences.
    Type: Grant
    Filed: June 28, 2001
    Date of Patent: June 4, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Eric S. Tosaya
  • Patent number: 5414222
    Abstract: An improved multilayer integrated circuit package. The package, which has a plurality of layers of conducting leads, has metal vias which connects leads in a first layer connected to leads in a second layer. The improvement comprises having at least on of the vias with a cross-section such that the via is much larger in a first direction than in a second direction generally perpendicular to the first direction.
    Type: Grant
    Filed: August 17, 1993
    Date of Patent: May 9, 1995
    Assignee: LSI Logic Corporation
    Inventors: Bidyut K. Sen, Eric S. Tosaya
  • Patent number: 5304743
    Abstract: An improved multilayer integrated circuit package. The package, which has a plurality of layers of conducting leads, has metal vias which connects leads in a first layer connected to leads in a second layer. The improvement comprises having at least one of the vias with a cross-section such that the via is much larger in a first direction than in a second direction generally perpendicular to said first direction.
    Type: Grant
    Filed: May 12, 1992
    Date of Patent: April 19, 1994
    Assignee: LSI Logic Corporation
    Inventors: Bidyut K. Sen, Eric S. Tosaya
  • Patent number: 4810671
    Abstract: An improved method for eutectically bonding a silicon wafer onto a gold preform is described. A gold/silicon seed is placed on a pure gold preform. Then a die is placed onto the pure gold preform and the gold/silicon seed, wherein the seed acts as a catalyst to form an eutectic bond.
    Type: Grant
    Filed: March 14, 1988
    Date of Patent: March 7, 1989
    Assignee: Intel Corporation
    Inventors: Bidyut K. Bhattacharyya, Eric S. Tosaya
  • Patent number: 4771018
    Abstract: An improved method for eutectically bonding a silicon wafer onto a gold preform is described. A gold/silicon seed is placed on a pure gold preform. Then a die is placed onto the pure gold preform and the gold/silicon seed, wherein the seed acts as a catalyst to form an eutectic bond.
    Type: Grant
    Filed: March 19, 1987
    Date of Patent: September 13, 1988
    Assignee: Intel Corporation
    Inventors: Bidyut K. Bhattacharyya, Eric S. Tosaya