Patents by Inventor Eric Sagnard

Eric Sagnard has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SYSTEM AND METHOD FOR LOADING A CORRECTIVE CODE
    Publication number: 20260170140
    Abstract: The present description concerns a method of loading code into a system and the associated system. In a first state of the system, the encrypted code is written into a volatile memory via a programming port. In a second state of the system, the encrypted code is loaded into a first circuit, where it is decrypted before being written into a one-time programmable memory. The system then switches to a third state. The one-time programmable memory area is programmable only by the first circuit and only in the second state.
    Type: Application
    Filed: December 11, 2025
    Publication date: June 18, 2026
    Inventors: Lionel Debieve, Loic Pallardy, Mark Trimmer, Eric Sagnard, Asma Mkhinini
  • Method for managing a return of a product for analysis and corresponding product
    Patent number: 11143701
    Abstract: A method for managing a product includes: placing an integrated circuit in a bootstrap mode with debugging prohibition in response to each reset or power-up of the integrated circuit and in an absence of a reception, on a test access port of the product, of a first command; and placing the integrated circuit in an analysis mode with debugging authorization in response to reception, on the test access port, of the first command following the reset or the power-up of the integrated circuit. Placing the integrated circuit in the analysis mode is maintained at least as long as a second command has not been received on the test access port. Placing the integrated circuit in the bootstrap mode and placing the integrated circuit in the analysis mode are performed in response to a determination that the integrated circuit has never before been placed in the analysis mode with debugging authorization.
    Type: Grant
    Filed: June 23, 2020
    Date of Patent: October 12, 2021
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Lionel Sinegre, Eric Sagnard, Stephan Courcambeck, William Orlando, Layachi Daineche
  • METHOD FOR MANAGING A RETURN OF A PRODUCT FOR ANALYSIS AND CORRESPONDING PRODUCT
    Publication number: 20200319247
    Abstract: A method for managing a product includes: placing an integrated circuit in a bootstrap mode with debugging prohibition in response to each reset or power-up of the integrated circuit and in an absence of a reception, on a test access port of the product, of a first command; and placing the integrated circuit in an analysis mode with debugging authorization in response to reception, on the test access port, of the first command following the reset or the power-up of the integrated circuit. Placing the integrated circuit in the analysis mode is maintained at least as long as a second command has not been received on the test access port. Placing the integrated circuit in the bootstrap mode and placing the integrated circuit in the analysis mode are performed in response to a determination that the integrated circuit has never before been placed in the analysis mode with debugging authorization.
    Type: Application
    Filed: June 23, 2020
    Publication date: October 8, 2020
    Inventors: Lionel Sinegre, Eric Sagnard, Stephan Courcambeck, William Orlando, Layachi Daineche
  • Method for managing a return of a product for analysis and corresponding product
    Patent number: 10705141
    Abstract: A method for managing a product includes: placing an integrated circuit in a bootstrap mode with debugging prohibition in response to each reset or power-up of the integrated circuit and in an absence of a reception, on a test access port of the product, of a first command; and placing the integrated circuit in an analysis mode with debugging authorization in response to reception, on the test access port, of the first command following the reset or the power-up of the integrated circuit. Placing the integrated circuit in the analysis mode is maintained at least as long as a second command has not been received on the test access port. Placing the integrated circuit in the bootstrap mode and placing the integrated circuit in the analysis mode are performed in response to a determination that the integrated circuit has never before been placed in the analysis mode with debugging authorization.
    Type: Grant
    Filed: October 10, 2018
    Date of Patent: July 7, 2020
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Lionel Sinegre, Eric Sagnard, Stephan Courcambeck, William Orlando, Layachi Daineche
  • METHOD FOR MANAGING A RETURN OF A PRODUCT FOR ANALYSIS AND CORRESPONDING PRODUCT
    Publication number: 20190107576
    Abstract: A method for managing a product includes: placing an integrated circuit in a bootstrap mode with debugging prohibition in response to each reset or power-up of the integrated circuit and in an absence of a reception, on a test access port of the product, of a first command; and placing the integrated circuit in an analysis mode with debugging authorization in response to reception, on the test access port, of the first command following the reset or the power-up of the integrated circuit. Placing the integrated circuit in the analysis mode is maintained at least as long as a second command has not been received on the test access port. Placing the integrated circuit in the bootstrap mode and placing the integrated circuit in the analysis mode are performed in response to a determination that the integrated circuit has never before been placed in the analysis mode with debugging authorization.
    Type: Application
    Filed: October 10, 2018
    Publication date: April 11, 2019
    Inventors: Lionel Sinegre, Eric Sagnard, Stephan Courcambeck, William Orlando, Layachi Daineche