Abstract: The detection circuit comprises a detector connected to an integration node. A bias circuit biases the detector between a first bias state and a second floating state. The potential of the integration node is at a target value when the bias circuit biases the detector to the first state and varies when the detector is in floating state. A measurement circuit without charge losses delivers a value representative of the potential present on the integration node N. A transfer circuit of the electric charges performs transfer of the electric charges from a stray capacitor of the photodiode to an integration capacitor. An output terminal delivers a voltage representative of the potential present on the second terminal of the first capacitor.

Abstract: The detection circuit comprises a detector connected to an integration node. A bias circuit biases the detector between a first bias state and a second floating state. The potential of the integration node is at a target value when the bias circuit biases the detector to the first state and varies when the detector is in floating state. A measurement circuit without charge losses delivers a value representative of the potential present on the integration node N. A transfer circuit of the electric charges performs transfer of the electric charges from a stray capacitor of the photodiode to an integration capacitor. An output terminal delivers a voltage representative of the potential present on the second terminal of the first capacitor.

Abstract: An electromagnetic radiation detection circuit includes a photodetector transforming the received electromagnetic radiation into an electric current. A readout circuit is coupled to a first terminal of the photodetector and configured to transform a current signal into a voltage signal. A capacitor has a first terminal electrically coupled to the first terminal of the photodetector and a second terminal electrically coupled to the readout circuit. A resistor has a first terminal electrically coupled to the capacitor and to a first terminal of the photodetector. A bias circuit is electrically coupled to a second terminal of the resistor and configured to bias the photodetector during a first time period by means of the resistor.

Abstract: An electromagnetic radiation detection circuit includes a photodetector transforming the received electromagnetic radiation into an electric current. A bias circuit is connected to the photodetector. An amplifying circuit has an input terminal coupled to the photodetector. An amplifying transistor has a first low-impedance electrode forming the input terminal of the amplifying circuit and a second low-impedance electrode coupled to an output terminal of the detection circuit. The transistor is configured to conduct the current applied on the first electrode. A high-impedance electric load is connected to the second electrode to deliver a voltage representative of the electric current originating from the photodetector.

Abstract: A pixel matrix is arranged in line of pixels. Each pixel is either in a first state or in a second state. The matrix mainly contains pixels in the second state. Each line of pixels is tested in order to determine whether it contains or not a pixel in a first state. The result from this test for each line is sent into a receiver. The lines including at least one pixel in the first state are more accurately analyzed in order to determine the position of this or these pixel in the line.

Abstract: An electromagnetic radiation detection circuit includes a photodetector transforming the received electromagnetic radiation into an electric current. A readout circuit is coupled to a first terminal of the photodetector and configured to transform a current signal into a voltage signal. A capacitor has a first terminal electrically coupled to the first terminal of the photodetector and a second terminal electrically coupled to the readout circuit. A resistor has a first terminal electrically coupled to the capacitor and to a first terminal of the photodetector. A bias circuit is electrically coupled to a second terminal of the resistor and configured to bias the photodetector during a first time period by means of the resistor.

Abstract: A pixel matrix is arranged in line of pixels. Each pixel is either in a first state or in a second state. The matrix mainly contains pixels in the second state. Each line of pixels is tested in order to determine whether it contains or not a pixel in a first state. The result from this test for each line is sent into a receiver. The lines including at least one pixel in the first state are more accurately analyzed in order to determine the position of this or these pixel in the line.

Abstract: An electromagnetic radiation detection circuit includes a photodetector transforming the received electromagnetic radiation into an electric current. A bias circuit is connected to the photodetector. An amplifying circuit has an input terminal coupled to the photodetector. An amplifying transistor has a first low-impedance electrode forming the input terminal of the amplifying circuit and a second low-impedance electrode coupled to an output terminal of the detection circuit. The transistor is configured to conduct the current applied on the first electrode. A high-impedance electric load is connected to the second electrode to deliver a voltage representative of the electric current originating from the photodetector.

Abstract: The detection circuit of the Source Follower per Detector type comprises a photodiode connected to an integration node. A biasing circuit makes it possible to bias the photodiode between a first reverse-bias state and a second floating state. A readout circuit is connected to the integration node for generating a signal representative of the scene observed by the photodiode. A metal shielding is arranged around the integration node. The metal shielding is connected to an output of the readout circuit configured to have a potential varying in the same direction as the potential at the integration node.

Abstract: The detection circuit of the Source Follower per Detector type comprises a photodiode connected to an integration node. A biasing circuit makes it possible to bias the photodiode between a first reverse-bias state and a second floating state. A readout circuit is connected to the integration node for generating a signal representative of the scene observed by the photodiode. A metal shielding is arranged around the integration node. The metal shielding is connected to an output of the readout circuit configured to have a potential varying in the same direction as the potential at the integration node.

Abstract: A method of reading electrical charges produced by a photo-detector of a photo-detector matrix includes collecting and storing electrical charges produced by the photo-detector in a first capacitive element, transferring the charges stored in the first capacitive element to a second capacitive element, and reading the voltage at the terminals of the second capacitive element. The transfer followed by the reading is carried out in at least two phases: at least one first phase taking place during the collection and storage of the charges in the first capacitive element, and a second phase taking place at the end of the collection and storage of the electrical charges in the first capacitive element.

Abstract: A device for reading electric currents including a capacitive element to integrate the current, the terminals of the capacitive element being connected to the mass and to an output branch of the device respectively, and a differential pair including: a first transistor mounted between the input branch of the input stage and the capacitive element, the transistor being controlled by a polarized impulse voltage, capable of putting the first transistor alternately into the off state and then into the on state; and a second transistor mounted between the input branch of the input stage and a potential other than that of the capacitive element, said transistor also being controlled by a polarized impulse voltage, capable of putting the second transistor alternately into the off state and then into the on state, wherein the second transistor is mounted in phase opposition relative to the first transistor.

Abstract: A method of reading electrical charges produced by a photo-detector of a photo-detector matrix includes collecting and storing electrical charges produced by the photo-detector in a first capacitive element, transferring the charges stored in the first capacitive element to a second capacitive element, and reading the voltage at the terminals of the second capacitive element. The transfer followed by the reading is carried out in at least two phases: at least one first phase taking place during the collection and storage of the charges in the first capacitive element, and a second phase taking place at the end of the collection and storage of the electrical charges in the first capacitive element.

Abstract: A device for reading electric currents including a capacitive element to integrate the current, the terminals of the capacitive element being connected to the mass and to an output branch of the device respectively, and a differential pair including: a first transistor mounted between the input branch of the input stage and the capacitive element, the transistor being controlled by a polarized impulse voltage, capable of putting the first transistor alternately into the off state and then into the on state; and a second transistor mounted between the input branch of the input stage and a potential other than that of the capacitive element, said transistor also being controlled by a polarized impulse voltage, capable of putting the second transistor alternately into the off state and then into the on state, wherein the second transistor is mounted in phase opposition relative to the first transistor.

Abstract: The invention concerns an active TFT matrix for optical sensor comprising a substrate, a TFT transistor matrix formed on said substrate, a set of transistor control lines (3): a conductor level (4) according to a specific pattern forming an electrode array (5), each electrode (5) defining a zone called pixel: a set of columns (10) for load transfer between the electrodes (5) and an external electronics. The pixel electrode (5) is located entirely inside an outline delimited by two lines (3) and two successive columns (10), a protective gap (g1, g2) being provided between the inside edge of said outline and the periphery of the pixel (5) such that the pixel electrode (5) does not cover either the lines (3) or the columns (10).

Abstract: The invention concerns an active TFT matrix for optical sensor comprising a substrate, a TFT transistor matrix formed on said substrate, a set of transistor control lines (3): a conductor level (4) according to a specific pattern forming an electrode array (5), each electrode (5) defining a zone called pixel: a set of columns (10) for load transfer between the electrodes (5) and an external electronics. The pixel electrode (5) is located entirely inside an outline delimited by two lines (3) and two successive columns (10), a protective gap (g1, g2) being provided between the inside edge of said outline and the periphery of the pixel (5) such that the pixel electrode (5) does not cover either the lines (3) or the columns (10).

Abstract: The present invention relates to a method for addressing a flat screen composed of lines and columns, with pixels located at their intersections, characterized in that, at the start of each sampling of the video signal to be displayed on the screen, a voltage (Vr) higher than the working voltage range (V) is applied to the selected pixel for a time tr, then the working voltage is sampled for a time ts.

Abstract: A shift register having several cascaded stages, each stage containing an output at a first node connected to a next stage, a first input connected to an output of a preceding stage, a second input connected to an output of the next stage and a first terminal connected to a first clock signal and a second terminal connected to a second clock signal, the stage containing a first semiconductor device switching the output of the stage between high and low values of the first clock signal, the first semiconductor device being controlled by the potential of a second node, itself connected to the output of the preceding stage across a second semiconductor device controlled by the output of the preceding stage; to a negative potential across a third semiconductor device controlled by the output of the next stage; and to the second terminal connected to the second clock signal across a first capacitance, wherein a second capacitance is mounted between the second node and the output of the next stage.

Abstract: The present invention can be used to make integrated circuits on the same substrate as the active matrix owing to the possibility that it offers of connecting transistor gates to sources or drains of the same or other transistors, and thus be used in a "integrated drivers" technology. It is also possible to make different types of transistors and capacitances using this method, without adding any additional mask levels.