Abstract: This disclosure describes techniques that include performing cryptographic operations (encryption, decryption, generation of a message authentication code). Such techniques may involve the data processing unit performing any of multiple modes of encryption, decryption, and/or other cryptographic operation procedures or standards, including, Advanced Encryption Standard (AES) cryptographic operations. In some examples, the security block is implemented as a unified, multi-threaded, high-throughput encryption and decryption system for performing multiple modes of AES operations.

Abstract: This disclosure describes techniques that include performing cryptographic operations (encryption, decryption, generation of a message authentication code). Such techniques may involve the data processing unit performing any of multiple modes of encryption, decryption, and/or other cryptographic operation procedures or standards, including, Advanced Encryption Standard (AES) cryptographic operations. In some examples, the security block is implemented as a unified, multi-threaded, high-throughput encryption and decryption system for performing multiple modes of AES operations.

Abstract: An example processing device includes a memory including a discreet finite automata (DFA) buffer configured to store at least a portion of a DFA graph, the DFA graph comprising a plurality of nodes, each of the nodes having zero or more arcs each including a respective label and pointing to a respective subsequent node of the plurality of nodes, at least one of the plurality of nodes comprising a match node, wherein the at least portion of the DFA graph comprises one or more slots of a memory slice, the one or more slots comprising data representing one or more of the arcs for at least one node of the plurality of nodes, and a DFA engine implemented in circuitry, the DFA engine comprising one or more DFA threads implemented in circuitry and configured to evaluate a payload relative to the DFA graph.

Abstract: This disclosure describes techniques that include performing cryptographic operations (encryption, decryption, generation of a message authentication code). Such techniques may involve the data processing unit performing any of multiple modes of encryption, decryption, and/or other cryptographic operation procedures or standards, including, Advanced Encryption Standard (AES) cryptographic operations. In some examples, the security block is implemented as a unified, multi-threaded, high-throughput encryption and decryption system for performing multiple modes of AES operations.

Abstract: A DFA engine is described that determines whether a current symbol of a payload matches a label of any effective arcs or negative arcs associated with a current node of a DFA graph that are stored in a cache. Responsive to determining that the current symbol does not match a label of any effective or negative arcs associated with the current node of the DFA graph, the DFA engine determines whether the current symbol matches a label of any arc associated with the current node of the DFA graph that is stored in a memory. Responsive to determining that the current symbol matches a label of a particular arc associated with the current node of the DFA graph that is stored in the memory, the DFA engine stores the particular arc in the cache as a new effective arc and uses the particular arc to evaluate the current symbol.

Abstract: This disclosure describes techniques that include performing cryptographic operations (encryption, decryption, generation of a message authentication code). Such techniques may involve the data processing unit performing any of multiple modes of encryption, decryption, and/or other cryptographic operation procedures or standards, including, Advanced Encryption Standard (AES) cryptographic operations. In some examples, the security block is implemented as a unified, multi-threaded, high-throughput encryption and decryption system for performing multiple modes of AES operations.

Abstract: A DFA engine is described that determines whether a current symbol of a payload matches a label of any effective arcs or negative arcs associated with a current node of a DFA graph that are stored in a cache. Responsive to determining that the current symbol does not match a label of any effective or negative arcs associated with the current node of the DFA graph, the DFA engine determines whether the current symbol matches a label of any arc associated with the current node of the DFA graph that is stored in a memory. Responsive to determining that the current symbol matches a label of a particular arc associated with the current node of the DFA graph that is stored in the memory, the DFA engine stores the particular arc in the cache as a new effective arc and uses the particular arc to evaluate the current symbol.

Abstract: An example processing device includes a memory including a discreet finite automata (DFA) buffer configured to store at least a portion of a DFA graph, the DFA graph comprising a plurality of nodes, each of the nodes having zero or more arcs each including a respective label and pointing to a respective subsequent node of the plurality of nodes, at least one of the plurality of nodes comprising a match node, wherein the at least portion of the DFA graph comprises one or more slots of a memory slice, the one or more slots comprising data representing one or more of the arcs for at least one node of the plurality of nodes, and a DFA engine implemented in circuitry, the DFA engine comprising one or more DFA threads implemented in circuitry and configured to evaluate a payload relative to the DFA graph.