Abstract: A discrete-time harmonic rejection mixer, an input device, and methods for using the same are described herein. In one example, a discrete-time harmonic rejection mixer includes a switched-capacitor network and a switch controller. The switched-capacitor network includes first, second, and third switched capacitor sub-circuits, each including a pair of capacitors and a set of switches. The switch controller is coupled to the switched-capacitor network, and is configured to operate the sets of switches. More specifically, the switch controller is configured to operate the sets of switches in an out of phase manner to produce the harmonic rejection effect. Capacitance values for the first pair of capacitors are roughly equal to capacitance values for the third pair of capacitors. An input device, method, and harmonic rejection circuit exhibiting the above features are provided as examples.

Abstract: Embodiments described herein include an input device, processing system, and method of performing capacitive sensing using an input device comprising a first plurality of sensor electrodes, a second plurality of sensor electrodes, and a plurality of display electrodes. The method comprises, during a first period, driving the first plurality of sensor electrodes with a first absolute capacitive sensing signal to receive first resulting signals, and driving the second plurality of sensor electrodes and the plurality of display electrodes with a first guarding signal. Each of the first plurality of sensor electrodes comprises at least one common electrode of a display, and wherein each common electrode is configured to be driven for display updating and for capacitive sensing.

Abstract: This disclosure generally provides an input device that includes a matrix sensor that includes a plurality of sensor electrodes arranged in rows on a common surface or plane. The input device may include a plurality of sensor modules coupled to the sensor electrodes that measure capacitive sensing signals corresponding to the electrodes. Instead of measuring sensor electrodes that are in the same column, the embodiments herein simultaneously measure capacitive sensing signals on at least two sensor electrodes that are in the same row. In one example, the sensor electrodes in the row being measured are spaced the same distance from a side of a substrate coupling the electrodes to the sensor modules and may have approximately the same electrical time constant.

Abstract: Embodiments described herein include an input device with a plurality of capacitive sensor electrodes configured to receive a signal. The input device also includes a processing system coupled to the plurality of capacitive sensor electrodes. The processing system includes an analog front end (AFE). The AFE includes an anti-aliasing filter comprising a continuous time analog infinite impulse response (IIR) filter configured to filter out interference from the received signal at frequencies higher than a signal frequency of the processing system to produce an anti-aliased signal. The AFE also includes a charge integrator configured to integrate the anti-aliased signal.

Abstract: The embodiments herein are generally directed to using a current-mode CBC circuit to maintain a voltage bias setting at a receiver when performing capacitive sensing. To do so, the CBC circuit may compensate for the change in voltage at a receiver by providing a current at the input of the receiver. Instead of using a passive CBC capacitor for each receiver, the input device may use a single CBC capacitor and a plurality of current mirrors to source and sink the current required to correct the input voltage at a plurality of receivers. As a result, the current-mode CBC circuit includes only one passive capacitor (or bank of capacitors) and a plurality of current mirrors which may provide space and cost benefits relative to a CBC circuit that uses a passive capacitor (or bank of capacitors) for each receiver channel.

Abstract: Disclosed herein are techniques related to a discrete-time harmonic rejection mixer. The discrete-time harmonic rejection mixer includes a switched-capacitor network and a switch controller. The switched-capacitor network includes first, second, and third switched capacitor sub-circuits, each including a pair of capacitors and a set of switches. The switch controller is coupled to the switched-capacitor network, and is configured to operate the sets of switches. More specifically, the switch controller is configured to operate the sets of switches in an out of phase manner to produce the harmonic rejection effect. Capacitance values for the first pair of capacitors are roughly equal to capacitance values for the third pair of capacitors. An input device, method, and harmonic rejection circuit exhibiting the above features are provided as examples.

Abstract: Embodiments include a method (as well as an input device and processing system) that includes driving a display signal onto at least one of a plurality of display electrodes for updating a display, and driving an input sensing signal onto at least one of a plurality of sensor electrodes, where driving the input sensing and driving the display signal at least partially overlap in time. The method further includes receiving, using a coupling electrode disposed proximate to the at least one display electrode, a coupling signal that represents an effect of a signal on at least one of the display electrodes, on a signal on at least one of the sensor electrodes, acquiring resulting signals with at least one of the sensor electrodes, and adjusting the resulting signals based on the coupling signal.

Abstract: Embodiments include a method (as well as an input device and processing system) that includes driving a display signal onto at least one of a plurality of display electrodes for updating a display, and driving an input sensing signal onto at least one of a plurality of sensor electrodes, where driving the input sensing and driving the display signal at least partially overlap in time. The method further includes receiving, using a coupling electrode disposed proximate to the at least one display electrode, a coupling signal that represents an effect of a signal on at least one of the display electrodes, on a signal on at least one of the sensor electrodes, acquiring resulting signals with at least one of the sensor electrodes, and adjusting the resulting signals based on the coupling signal.

Abstract: The embodiments herein are generally directed to using a current-mode CBC circuit to maintain a voltage bias setting at a receiver when performing capacitive sensing. To do so, the CBC circuit may compensate for the change in voltage at a receiver by providing a current at the input of the receiver. Instead of using a passive CBC capacitor for each receiver, the input device may use a single CBC capacitor and a plurality of current mirrors to source and sink the current required to correct the input voltage at a plurality of receivers. As a result, the current-mode CBC circuit includes only one passive capacitor (or bank of capacitors) and a plurality of current mirrors which may provide space and cost benefits relative to a CBC circuit that uses a passive capacitor (or bank of capacitors) for each receiver channel.

Abstract: Embodiments of the invention are generally directed to improving the slew rate of an amplifier as the amplifier charges or discharges a capacitive load. In one embodiment, the amplifier is coupled to a slew-enhancing circuit which uses a control signal from the amplifier to aid the amplifier when charging or discharging the load. For example, the control signal may be an internal voltage used by the amplifier to control circuit elements within the amplifier. By routing the control signal to the slew-enhancing circuit, the control signal biases the circuit elements within the slew-enhancing circuit to source a boost current when charging the capacitive load or sink the boost current when discharging the capacitive load.

Abstract: Embodiments of the invention are generally directed to improving the slew rate of an amplifier as the amplifier charges or discharges a capacitive load. In one embodiment, the amplifier is coupled to a slew-enhancing circuit which uses a control signal from the amplifier to aid the amplifier when charging or discharging the load. For example, the control signal may be an internal voltage used by the amplifier to control circuit elements within the amplifier. By routing the control signal to the slew-enhancing circuit, the control signal biases the circuit elements within the slew-enhancing circuit to source a boost current when charging the capacitive load or sink the boost current when discharging the capacitive load.

Abstract: Embodiments of the invention generally provide generating a ZTC current using resistors that may be integrated into an IC, even if these resistors vary with temperature. Specifically, instead of applying a bandgap voltage across a ZTC resistor, the bandgap voltage may be applied to a temperature-dependent resistor to generate a first current that varies (either proportionally or complementary) with temperature. Additionally, a second current may be generated which compensates for the temperature variance of the first current. If the two currents change in the same manner relative to temperature (i.e., the respective slopes of the currents are the same when the underlying circuit elements are exposed to the same temperature variations), the difference between the currents remains constant. Thus, subtracting the two currents, regardless of the current temperature, results in a ZTC current—i.e., a current that is independent of temperature variations.