Patents by Inventor Eric SEGURA

Eric SEGURA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10783105
    Abstract: This communication network (18) extends between a plurality of input blocks (E1, . . . , EN1) comprising a predetermined number P1 of input ports and a plurality of output blocks (S1, . . . , SN2) comprising at least the same number P2 of output ports as the predetermined number P1. In this network, when the result of the multiplication of the number of input ports P1 by the number of input blocks N1 is even, the number N3 of switches is equal to: N ? ? 3 = N ? ? 1 × P ? ? 1 2 , and when the result of said multiplication is odd, the number N3 of switches is equal to: N ? ? 3 = N ? ? 1 × P ? ? 1 - 1 2 , and, for each switch, the first (30) and second (32) input terminals are each connected to different input blocks (E1, . . . , EN1) and the first (34) and second (36) output terminals are each connected to different output blocks (S1, . . . , SN2).
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: September 22, 2020
    Assignee: THALES
    Inventors: Eric Segura, Jean-Jacques Julié
  • Patent number: 10666577
    Abstract: This communication network (18) extends between a plurality of input blocks (E1, . . . , EN1) including a predetermined number P1 of input ports, multiple of the number N1 of input blocks, and a plurality of output blocks (S1, . . . , SN2), each output block including a number P2 of output ports (Z1, . . . , ZP2) greater than or equal to the predetermined number of input ports. In this network, when the number P1 of input ports is even, the number N3 of switches is equal to: N ? ? 3 = N ? ? 1 × P ? ? 1 2 , and when the number P1 is odd, the number N3 of switches is equal to: N ? ? 3 = N ? ? 1 P ? ? 1 × P ? ? 1 2 - 1 2 , and, for each switch, the first (30) and second (32) input terminals are each connected to different input blocks and the first (34) and second (36) output terminals are each connected to different output blocks.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: May 26, 2020
    Assignee: THALES
    Inventors: Eric Segura, Jean-Jacques Julié
  • Publication number: 20190081908
    Abstract: This communication network (18) extends between a plurality of input blocks (E1, . . . , EN1) including a predetermined number P1 of input ports, multiple of the number N1 of input blocks, and a plurality of output blocks (S1, . . . , SN2), each output block including a number P2 of output ports (Z1, . . . , ZP2) greater than or equal to the predetermined number of input ports. In this network, when the number P1 of input ports is even, the number N3 of switches is equal to: N ? ? 3 = N ? ? 1 × P ? ? 1 2 , and when the number P1 is odd, the number N3 of switches is equal to: N ? ? 3 = N ? ? 1 P ? ? 1 × P ? ? 1 2 - 1 2 , and, for each switch, the first (30) and second (32) input terminals are each connected to different input blocks and the first (34) and second (36) output terminals are each connected to different output blocks.
    Type: Application
    Filed: August 29, 2018
    Publication date: March 14, 2019
    Inventors: Eric SEGURA, Jean-Jacques JULIÉ
  • Publication number: 20190079889
    Abstract: This communication network (18) extends between a plurality of input blocks (E1, . . . , EN1) including a predetermined number P1 of input ports and a plurality of output blocks (S1, . . . , SN2) including at least the same number P2 of output ports as the predetermined number P1. In this network, when the result of the multiplication of the number of input ports P1 by the number of input blocks N1 is even, the number N3 of switches is equal to: N ? ? 3 = N ? ? 1 × P ? ? 1 2 , and when the result of the multiplication is odd, the number N3 of switches is equal to: N ? ? 3 = N ? ? 1 × P ? ? 1 - 1 2 , and, for each switch, the first (30) and second (32) input terminals are each connected to different input blocks (E1, . . . , EN1) and the first (34) and second (36) output terminals are each connected to different output blocks (S1, . . . , SN2).
    Type: Application
    Filed: August 29, 2018
    Publication date: March 14, 2019
    Inventors: Eric SEGURA, Jean-Jacques JULIÉ