Patents by Inventor Eric Soenen

Eric Soenen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220302089
    Abstract: A three-dimensional integrated circuit (3D IC) package is provided. The 3D IC package includes: a cache die including a low-dropout (LDO) regulator and a cache memory device; a compute die above the cache die, the compute die including a processor; and one or more first interconnect structures connecting the cache die and the compute die in a vertical direction.
    Type: Application
    Filed: December 22, 2021
    Publication date: September 22, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Stefan Rusu, Mohammed Rabiul Islam, Eric Soenen
  • Patent number: 11438007
    Abstract: An analog-to-digital converter (“ADC”) includes an input terminal configured to receive an analog input signal. A first ADC circuit is coupled to the input terminal and includes a VCO. The first ADC circuit is configured to output a first digital signal in a frequency domain based on the analog input signal. The first digital signal includes an error component. A first DAC is configured to convert the first digital signal to an analog output signal. A first summation circuit is configured to receive the analog output signal, the analog input signal, and a loop filtered version of the analog input signal and extract the error component, and output a negative of the error component. A second ADC circuit is configured to convert the negative of the error component to a digital error signal. A second summation circuit is configured to receive the first digital signal and the digital error signal, and to output a digital output signal corresponding to the analog input at an output terminal.
    Type: Grant
    Filed: February 22, 2021
    Date of Patent: September 6, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Martin Kinyua, Eric Soenen
  • Patent number: 11424724
    Abstract: An amplifier includes an input circuit configured to receive an analog input signal and a feedback signal, and output an analog error signal based on the analog input signal and the feedback signal. An ADC is configured to convert the analog error signal into a digital signal in a phase domain. A digital control circuit is configured to generate a digital control signal based on the digital signal in the phase domain. An output circuit is configured to generate an amplified output signal based on the digital control signal, and a feedback circuit is configured generate the feedback signal based on the amplified output signal.
    Type: Grant
    Filed: December 31, 2019
    Date of Patent: August 23, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Martin Kinyua, Eric Soenen
  • Publication number: 20220239302
    Abstract: An apparatus and method for analog to digital conversion of analog input signals are disclosed herein. In some embodiments, an analog-to-digital (ADC) may comprise: a first successive approximation register (SAR) circuit comprising a fast SAR (FSAR) circuit and a residue digital-to-analog converter (RDAC) circuit and a residue amplifier circuit, coupled to the RDAC circuit, comprising an amplifier circuit that is configured to amplify a residual signal generated by the RDAC circuit, wherein the amplifier circuit comprises a deadzone control circuit and a first, second and third inverter stages, wherein the third stage is biased to operate in a sub-threshold region.
    Type: Application
    Filed: April 11, 2022
    Publication date: July 28, 2022
    Inventors: Martin KINYUA, Eric SOENEN
  • Publication number: 20220239307
    Abstract: An analog-to-digital converter (ADC) includes a first ADC stage with a first sub-ADC stage configured to sample the analog input voltage in response to a first phase clock signal and output a first digital value corresponding to an analog input voltage in response to a second phase clock signal. A current mode DAC stage is configured to convert the analog input voltage and the first digital value to respective first and second current signals, determine a residue current signal representing a difference between the first and the second current signal, and convert the residue current signal to an analog residual voltage signal. A second ADC stage is coupled to the first ADC stage to receive the analog residual voltage signal, and convert the analog residue voltage signal to a second digital value. An alignment and digital error correction stage is configured to combine the first and the second digital values.
    Type: Application
    Filed: April 11, 2022
    Publication date: July 28, 2022
    Inventors: Martin Kinyua, Eric Soenen
  • Publication number: 20220208953
    Abstract: Various magnetic thin film inductor structures are disclosed that include one or more magnetic thin film (MTF) materials. During operation, an electric field passes through one or more conductive windings which, in turn, generates a magnetic field for storing energy within these magnetic thin film inductor structures. The magnetic thin film (MTF) materials within these magnetic thin film inductor structures effectively attract magnetic flux lines of this magnetic field. As a result, any magnetic leakage resulting from the magnetic field generated by these magnetic thin film inductor structures onto nearby electrical, mechanical, and/or electro-mechanical devices is lessened when compared to magnetic leakage resulting from the magnetic field generated by other inductor structures not having the one or more MTF materials.
    Type: Application
    Filed: March 21, 2022
    Publication date: June 30, 2022
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Alan ROTH, Eric Soenen, Paul Rannuci
  • Publication number: 20220158556
    Abstract: A power converter module includes a ground terminal, an input voltage terminal configured to receive a raw input voltage, and an interconnection terminal configured to provide a regulated output voltage to a load such as a SOC or SIP system to be powered. A voltage regulator is connected to the ground terminal and the input voltage terminal. An inductor has an inductor output connected to the interconnection terminal.
    Type: Application
    Filed: February 1, 2022
    Publication date: May 19, 2022
    Inventors: Ying-Chih Hsu, Eric Soenen, Alan Roth
  • Patent number: 11329659
    Abstract: An apparatus and method for analog to digital conversion of analog input signals are disclosed herein. In some embodiments, an analog-to-digital (ADC) may comprise: a first successive approximation register (SAR) circuit comprising a fast SAR (FSAR) circuit and a residue digital-to-analog converter (RDAC) circuit and a residue amplifier circuit, coupled to the RDAC circuit, comprising an amplifier circuit that is configured to amplify a residual signal generated by the RDAC circuit, wherein the amplifier circuit comprises a deadzone control circuit and a first, second and third inverter stages, wherein the third stage is biased to operate in a sub-threshold region.
    Type: Grant
    Filed: January 11, 2021
    Date of Patent: May 10, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Martin Kinyua, Eric Soenen
  • Publication number: 20220139607
    Abstract: An integrated transformer is disclosed. The integrated transformer includes a magnetic core situated in a first layer from among multiple layers of a semiconductor layer stack, a first conductor and a second conductor from among multiple conductors, and a via. The first conductor is situated within a second layer, above the first layer, from among the multiple layers of the semiconductor layer stack. The second conductor is situated within a third layer, below the first layer, from among the multiple layers of the semiconductor layer stack. The via physically and electrically connects the first conductor and the second conductor. The via, the first conductor, and the second conductor form a primary winding of the integrated transformer. The integrated transformer additionally includes a secondary winding, wrapped around the magnetic core, situated in the first layer, the second layer, and the third layer.
    Type: Application
    Filed: January 14, 2022
    Publication date: May 5, 2022
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Alan Roth, Eric Soenen
  • Patent number: 11303292
    Abstract: An analog-to-digital converter (ADC) includes a first ADC stage with a first sub-ADC stage configured to sample the analog input voltage in response to a first phase clock signal and output a first digital value corresponding to an analog input voltage in response to a second phase clock signal. A current steering DAC stage is configured to convert the analog input voltage and the first digital value to respective first and second current signals, determine a residue current signal representing a difference between the first and the second current signal, and convert the residue current signal to an analog residual voltage signal. A second ADC stage is coupled to the first ADC stage to receive the analog residual voltage signal, and convert the analog residue voltage signal to a second digital value. An alignment and digital error correction stage is configured to combine the first and the second digital values.
    Type: Grant
    Filed: December 14, 2020
    Date of Patent: April 12, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Martin Kinyua, Eric Soenen
  • Patent number: 11282916
    Abstract: Various magnetic thin film inductor structures are disclosed that include one or more magnetic thin film (MTF) materials. During operation, an electric field passes through one or mare conductive windings which, in turn, generates a magnetic field for storing energy within these magnetic thin film inductor structures. The magnetic thin film (MTF) materials within these magnetic thin film inductor structures effectively attract magnetic flux lines of this magnetic field. As a result, any magnetic leakage resulting from the magnetic field generated by these magnetic thin film inductor structures onto nearby electrical, mechanical, and/or electro-mechanical devices is lessened when compared to magnetic leakage resulting from the magnetic field generated by other inductor structures not having the one or more MTF materials.
    Type: Grant
    Filed: January 29, 2018
    Date of Patent: March 22, 2022
    Inventors: Alan Roth, Eric Soenen, Paul Ranucci
  • Patent number: 11271482
    Abstract: A DC-DC converter and a DC-DC converter operation method are provided. The DC-DC converter includes a power stage, an error amplifier, a pulse width modulation (PWM) generator, and a gate controller. The power stage includes a first transistor and a second transistor. The voltage dividers are configured to perform a voltage division on a first node of the power stage and a second node to generate a first voltage and a second voltage. The first node is an output node of the DC-DC converter and the second node is a node between the first transistor and the second transistor of the DC-DC converter. The comparator is configured to compare the first voltage and the second voltage to generate a turn-on time signal of the first transistor according to a comparison result.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: March 8, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Chun Chang, Alan Roth, Eric Soenen, Ying-Chih Hsu
  • Patent number: 11245329
    Abstract: A power converter module includes a ground terminal, an input voltage terminal confirmed to receive a raw input voltage, and an interconnection terminal configured to provide a regulated output voltage to a load such as a SOC or SIP system to be powered. A voltage regulator is connected to the ground terminal and the input voltage terminal. An inductor has an inductor output connected to the interconnection terminal.
    Type: Grant
    Filed: February 21, 2018
    Date of Patent: February 8, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ying-Chih Hsu, Eric Soenen, Alan Roth
  • Patent number: 11227713
    Abstract: An integrated transformer can be fabricated to include multiple first conductors, a magnetic core, and multiple second conductors. The first conductor can be fabricated within a first layer of a semiconductor layer stack. The magnetic core can be fabricated within multiple second layers, below the first layer, of the semiconductor layer stack. The multiple second conductors can be fabricated within a third layer, below the second layer, of the semiconductor layer stack. The multiple first conductors can be connected to the multiple second conductors to form a primary winding of the integrated transformer. The integrated transformer can additionally include a coupling element to wrap around the magnetic core to form a secondary winding of the integrated transformer.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: January 18, 2022
    Inventors: Alan Roth, Eric Soenen
  • Patent number: 11204614
    Abstract: A current balance circuit including a current sensing front end for sensing an output signal from each of a plurality of switching regulators and a current sensor for receiving the sensed output signal and converting the sensed signal into a sensed current signal. The current balance circuit further includes a current averaging circuit for receiving the sensed output signals and determining an average current output for the plurality of switching regulators and a current difference circuit for receiving the average current value and the sensed current signals and determining a current difference for each of the plurality of switching regulators. A calibration circuit is included for receiving the current differences and calculating a calibration value corresponding to each of the plurality of switching regulators which provides an indication of how to adjust a current output of the plurality of switching regulators to balance the current across the plurality of switching regulators.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: December 21, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Ying-Chih Hsu, Alan Roth, Eric Soenen
  • Patent number: 11158448
    Abstract: An inductor is formed in an IC device packaging structure. The structure includes an encapsulating material, with a ferromagnetic core in the encapsulation material. A plurality of metal layers are provided in the encapsulation material forming an inductor coil extending around the ferromagnetic core so as to form an inductor.
    Type: Grant
    Filed: June 14, 2018
    Date of Patent: October 26, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Alan Roth, Eric Soenen, Ying-Chih Hsu, Nick Samra, Stefan Rusu
  • Patent number: 11152332
    Abstract: A device includes a semiconductor die. The semiconductor die has formed thereon a plurality of multi-phase voltage regulator modules of the same design formed on a common semiconductor substrate.
    Type: Grant
    Filed: September 24, 2020
    Date of Patent: October 19, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Nick Samra, Alan Roth, Eric Soenen, Stefan Rusu, Paul Ranucci
  • Publication number: 20210305996
    Abstract: An analog-to-digital converter (“ADC”) includes an input terminal configured to receive an analog input signal. A first ADC circuit is coupled to the input terminal and includes a VCO. The first ADC circuit is configured to output a first digital signal in a frequency domain based on the analog input signal. The first digital signal includes an error component. A first DAC is configured to convert the first digital signal to an analog output signal. A first summation circuit is configured to receive the analog output signal, the analog input signal, and a loop filtered version of the analog input signal and extract the error component, and output a negative of the error component. A second ADC circuit is configured to convert the negative of the error component to a digital error signal. A second summation circuit is configured to receive the first digital signal and the digital error signal, and to output a digital output signal corresponding to the analog input at an output terminal.
    Type: Application
    Filed: February 22, 2021
    Publication date: September 30, 2021
    Inventors: Martin Kinyua, Eric Soenen
  • Publication number: 20210266001
    Abstract: An apparatus and method for analog to digital conversion of analog input signals are disclosed herein. In some embodiments, an analog-to-digital (ADC) may comprise: a first successive approximation register (SAR) circuit comprising a fast SAR (FSAR) circuit and a residue digital-to-analog converter (RDAC) circuit and a residue amplifier circuit, coupled to the RDAC circuit, comprising an amplifier circuit that is configured to amplify a residual signal generated by the RDAC circuit, wherein the amplifier circuit comprises a deadzone control circuit and a first, second and third inverter stages, wherein the third stage is biased to operate in a sub-threshold region.
    Type: Application
    Filed: January 11, 2021
    Publication date: August 26, 2021
    Inventors: Martin KINYUA, Eric SOENEN
  • Publication number: 20210257910
    Abstract: Devices and methods are provided for controlling dead-time of a direct current to direct current (DC-DC) converter. A control circuit includes a first transistor having a source/drain terminal coupled to an output voltage of the DC-DC converter configured to provide current based on the output voltage. The control circuit also includes a digital up/down counter having an output terminal electrically coupled to an input terminal of a delay cell of the DC-DC converter. A current sensing circuit of the control circuit is electrically coupled to an input terminal of the digital up/down counter configured to receive the current and drive the digital up/down counter based on the current.
    Type: Application
    Filed: April 7, 2021
    Publication date: August 19, 2021
    Inventors: Chia-Chun Chang, Alan Roth, Eric Soenen, Tysh-Bin Liu