Abstract: A multi-phase buck-boost converter includes a first half-bridge circuit, a second half-bridge circuit, a third half-bridge circuit, and a control circuit. The first half-bridge circuit is coupled to a first inductor terminal. The second half-bridge circuit is coupled to a second inductor terminal. The third half-bridge circuit is coupled to a third inductor terminal, a system voltage terminal, and a battery terminal. The control circuit is coupled to the first half-bridge circuit, the second half-bridge circuit, and the third half-bridge circuit. The control circuit is configured to transition the first half-bridge circuit, the second half-bridge circuit, and the third half-bridge circuit from operation in a buck mode to operation in a buck-boost mode based on an off-time of the first half-bridge being less than a particular time.

Abstract: Aspects of the disclosure include a first sense transistor having a gate and a drain configured to couple in parallel with a high-side transistor and a source terminal coupled to a first node, and a second sense transistor having a gate and a drain configured to couple in parallel with a low-side transistor, and a source terminal coupled to a third node. The circuit further includes a first comparator circuit having a first input coupled to the first node, a second input coupled to a second node, and an output, a second comparator circuit having a first input coupled to the third node, a second input coupled to a ground node, and an output, and a logic circuit having first input coupled to the output of the first comparator circuit, a second input coupled to the output of the second comparator circuit, and an output.

Abstract: Aspects of the disclosure include a including a first sense transistor having a gate and a drain configured to couple in parallel with a high-side transistor and a source terminal coupled to a first node, and a second sense transistor having a gate and a drain configured to couple in parallel with a low-side transistor, and a source terminal coupled to a third node. The circuit further includes a first comparator circuit having a first input coupled to the first node, a second input coupled to a second node, and an output, a second comparator circuit having a first input coupled to the third node, a second input coupled to a ground node, and an output, and a logic circuit having first input coupled to the output of the first comparator circuit, a second input coupled to the output of the second comparator circuit, and an output.