Abstract: A digital phase lock loop (PLL) for maintaining synchronization with the phase of a received data signal including a preamble and an information-containing data frame, by incrementing a state machine through an internal cyclic count, each cycle thereof including a center count tending to coincide with center regions of the successive pulses and an edge count tending to coincide with edges of the successive pulses. The PLL selects a current sample of the signal whenever the internal count reaches the predetermined center count value. The state machine internal count is updated in accordance with a cumulative phase error obtained by summing the phase errors detected over successive edges between each edge and the corresponding center count. The interval over which the cumulative phase error is computed depends upon the number of received edges during the preamble and depends upon elapsed time during the data frame.

Abstract: PLL error margin is improved by a half clock of the internal PLL clock by resolving the ambiguity between the two samples nominally centered about the pulse center point. This is achieved by intelligently choosing between the two samples nearest the pulse center by exploiting information from the phase error. Specifically, the choice is made depending upon the sign of the phase error. The result is that the margin of error of the PLL is improved by a half clock period, since on the average the choice between each one of the two samples represents half of the total one-clock resolution limit of the system.

Abstract: A digital PLL's stability and immunity to jitter are improved by deriving the correction to the state machine count from an average over several computations of the phase error. The PLL stability is improved by retaining all of the phase errors measured during a succession of plural phase measurement intervals. The plurality of phase errors thus obtained are averaged together, and the state machine internal count is corrected (updated) in accordance with this average, rather than according to an instantaneous phase error. As a result, the performance of the PLL is less susceptible to jitter-induced temporary excursions in the phase error, a significant advantage.

Abstract: A digital PLL's stability and immunity to jitter are improved by deriving the correction to the state machine count from an average over several computations of the phase error, and re-initializing the computation of the phase error to the residual error remaining after the correction. The PLL stability is improved by retaining all of the phase errors measured during a succession of plural phase measurement intervals and by retaining the residual error in the next cycle of cumulative phase error. The plurality of phase errors thus obtained are averaged together starting from the residual error left over from the previous cycle, and the state machine internal count is corrected (updated) in accordance with this average, rather than according to an instantaneous phase error. As a result, the performance of the PLL is less susceptible to jitter-induced temporary excursions in the phase error, a significant advantage.