Abstract: Data stored in a memory circuit may be encrypted using client keys that need to be available for high-speed data processing and yet held securely to avoid unauthorized access to the encrypted data. A secure processor circuit in a processor-based system obtains client keys associated with client applications and generates secure key-encryption keys that are used to encrypt the client keys so the client keys can be securely stored in the memory circuit. In some examples, data keys for encrypting data blocks associated with the client application may be generated from the client key, encrypted by a data key-encryption key generated in the secure processor circuit, and stored in the memory circuit. In such examples, because the client keys and data keys are encrypted while in memory, they are safer from software attacks on the memory circuit, which improves the security of the encrypted data blocks.

Abstract: Data stored in a memory circuit may be encrypted using client keys that need to be available for high-speed data processing and yet held securely to avoid unauthorized access to the encrypted data. A secure processor circuit in a processor-based system obtains client keys associated with client applications and generates secure key-encryption keys that are used to encrypt the client keys so the client keys can be securely stored in the memory circuit. In some examples, data keys for encrypting data blocks associated with the client application may be generated from the client key, encrypted by a data key-encryption key generated in the secure processor circuit, and stored in the memory circuit. In such examples, because the client keys and data keys are encrypted while in memory, they are safer from software attacks on the memory circuit, which improves the security of the encrypted data blocks.

Abstract: Data stored in a memory circuit may be encrypted using client keys that need to be available for high-speed data processing and yet held securely to avoid unauthorized access to the encrypted data. A secure processor circuit in a processor-based system obtains client keys associated with client applications and generates secure key-encryption keys that are used to encrypt the client keys so the client keys can be securely stored in the memory circuit. In some examples, data keys for encrypting data blocks associated with the client application may be generated from the client key, encrypted by a data key-encryption key generated in the secure processor circuit, and stored in the memory circuit. In such examples, because the client keys and data keys are encrypted while in memory, they are safer from software attacks on the memory circuit, which improves the security of the encrypted data blocks.

Abstract: An exemplary memory interface circuit disclosed herein re-encrypts data in an encrypted data block in a memory circuit to further protect the data. In particular, the memory interface circuit reads an encrypted data block from the memory circuit and decrypts the encrypted data block using a first key that was previously used to encrypt the block of data. Then, the memory interface circuit encrypts the data again using a second key before storing the re-encrypted data back into the memory circuit. In some examples, the memory interface circuit includes a re-encryption circuit that includes secure configuration registers to control occasional re-encryption of the encrypted data in an effort to evade detection of the encryption key. In some examples, the time between re-encryptions may be adjusted in response to a frequency of memory accesses to the memory circuit.

Abstract: A video processing device (150) includes a bitstream accelerator module (106) and a video processing engine (108). The bitstream accelerator module (106) has an input for receiving a stream of encoded video data, and an output adapted to be coupled to a memory (112) for storing partially decoded video data. The bitstream accelerator module (106) partially decodes the stream of encoded video data according to a selected one of a plurality of video formats to provide the partially decoded video data. The video processing engine (108) has input adapted to be coupled to the memory (112) for reading the partially decoded video data, and an output for providing decoded video data.

Abstract: A method and device that allow picture slices of a Video stream to be processed in an order different than the order they were received is disclosed. Information mapping the location of picture slices that are stored in the order they were received is stored to allow subsequent processing to access the picture slice in any order, including render order.

Abstract: A method and device that allow picture slices of a video stream to be processed in an order different than the order they were received is disclosed. Information mapping the location of picture slices that are stored in the order they were received is stored to allow subsequent processing to access the picture slice in any order, including render order.

Abstract: A video processing apparatus and methodology use a combination of a processor and a video decoding hardware block to decode video data by using a reference block cache memory to perform motion compensation decode operations in the video decoding hardware block. To improve the cache hit rate, each memory access for required reference block(s) is used to fetch one or more additional reference blocks which can be used to improve the cache hit rate with future motion compensation operations. Speculative fetch control logic selects the additional reference blocks by using a frequency history table to accumulate compared motion vector information for a current motion compensation block with motion vector information from previously processed motion compensation blocks.

Abstract: A device is disclosed having a motion vector processing module to determine a first set of motion vectors associated with a macroblock of a video picture. A motion vector reduction module determines a second set of motion vectors, based on the first set of motion vectors, associated the macroblock, the second set having fewer motion vectors than the first set.

Abstract: A method and device that allow picture slices of a video stream to be processed in an order different than the order they were received is disclosed. Information mapping the location of picture slices that are stored in the order they were received is stored to allow subsequent processing to access the picture slice in any order, including render order.

Abstract: A video processing device (150) includes a bitstream accelerator module (106) and a video processing engine (108). The bitstream accelerator module (106) has an input for receiving a stream of encoded video data, and an output adapted to be coupled to a memory (112) for storing partially decoded video data. The bitstream accelerator module (106) partially decodes the stream of encoded video data according to a selected one of a plurality of video formats to provide the partially decoded video data. The video processing engine (108) has input adapted to be coupled to the memory (112) for reading the partially decoded video data, and an output for providing decoded video data.

Abstract: A device testing apparatus and method for testing a semiconductor device is provided. For device testing, stimulus data is generated and provided to the semiconductor device, and output data of the semiconductor device is then evaluated to verify proper operation of the semiconductor device. Further, data in the semiconductor device output data space is mapped to stimulus data, and a set of stimulus data is determined based on the mapping results for further testing.

Abstract: A computer system which is capable of transmitting information content through walls and other barriers to a remote station such as a home entertainment system. The system tests a plurality of radio frequency channels to locate a channel that is not in use. Channels that are in already in use are rejected to avoid interference with existing services. Once an unused channel is located, the computer system displays indicia of that channel to the user and transmits information content on the unused channel. The remote station receives the information content. In one embodiment, the remote station is a home entertainment system with audio amplifiers and speakers substantially larger and more powerful than those typically associated with computer systems such as personal and other computers. In this manner the audio and/or video qualities of the computer system are substantially enhanced by transmitting content to the remote system for presentation in an acoustically and/or visually enhanced environment.

Abstract: A computer system which is capable of transmitting information content through walls and other barriers to a remote station such as a home entertainment system. The system tests a plurality of radio frequency channels to locate a channel that is not in use. Channels that are in already in use are rejected to avoid interference with existing services. Once an unused channel is located, the computer system displays indicia of that channel to the user and transmits information content on the unused channel. The remote station receives the information content. In one embodiment, the remote station is a home entertainment system with audio amplifiers and speakers substantially larger and more powerful than those typically associated with computer systems such as personal and other computers. In this manner the audio and/or video qualities of the computer system are substantially enhanced by transmitting content to the remote system for presentation in an acoustically and/or visually enhanced environment.