Abstract: An H-tree is formed in a conducting layer over a base array of a structured ASIC, the H-tree being a predefined constraint imposed on ad hoc circuit designs adapted to make use of a base array and H-tree. The endpoints of an H-tree can be formed at or near sequential elements. When an H-tree is used as part of a clock structure, clock skew to sequential elements and consumption of routing resources for forming a clock structure can be minimized. When a pulse generator is coupled to an H-tree, at least one flip-flop of a plurality of flip-flops can be emulated with an individual latch, thereby increasing effective flip-flop density.

Abstract: An H-tree is formed in a conducting layer over the base array of a structured ASIC, the H-tree being a predefined constraint imposed on ad hoc circuit designs adapted to make use of the base array and H-tree. The endpoints of the H-tree are formed at or near sequential elements. When the H-tree is used as part of a clock structure, clock skew to the sequential elements is minimized as is the consumption of routing resources for forming the clock structure. When a pulse generator is coupled to the H-tree, individual flip-flops can be emulated with individual latches, thereby increasing the effective flip-flop density.

Abstract: An H-tree is formed in a conducting layer over a base array of a structured ASIC, an H-tree being a predefined constraint imposed on ad hoc circuit designs adapted to make use of the base array and H-tree. The endpoints of the H-tree are formed at or near sequential elements. When the H-tree is used as part of a clock structure, clock skew to the sequential elements is minimized as is the consumption of routing resources for forming the clock structure. When a pulse generator is coupled to the H-tree, each individual flip-flop of a plurality of flip-flops can be emulated with an individual latch, thereby increasing effective flip-flop density.

Abstract: A method operates a media access control device. The method includes (a) detecting the assertion of a flow control condition, (b) generating a PAUSE frame in response to the detection of a flow control condition, the PAUSE frame directing a remote device to PAUSE for a first amount of time, (c) causing the media access device to wait for a second amount of time, the second amount of time being less than or equal to the first amount of time, and (d) generating, upon expiration of the second amount of time and the continued assertion of the flow control condition, an additional PAUSE frame directing a remote device to PAUSE for a first amount of time.

Abstract: In a 100BASE-T4 protocol network, the “carrier_status” signal associated with an incoming packet on a PMA of a given port of a Clause 27 repeater is obviated and a direct connection between PMAs and a Clause 27 repeater in the network is eliminated by transmitting synthetic preamble signals over the PMA-Repeater Data Interface to the Clause 27 repeater corresponding to the given port at an early time prior to the time that the actual preamble information of the packet is transmitted over that data interface. Receipt of the synthetic preamble signals causes the repeater to awaken and to repeat the synthetic preamble signals to other ports of the repeater. In turn, the other ports become quiet in anticipation of data to be repeated from the given port to the other ports of the repeater.

Abstract: An apparatus and method for aligning any number of multiple parallel channels of data signals according to a single clock is provided. The synchronization process is accomplished through the use of a First-In-First-Out (FIFO) principle and individual storage elements implementing the FIFO principle for each received data channel. Each channel's data signals are read into a corresponding storage element, maintained in order, and read out upon the assertion of read signals in synchronization with a designated single clock signal. The apparatus and method preferably uses indications of data ready to be read from a storage element implementing the FIFO principle and the presence of a master clock signal to activate the reading of the data from the corresponding storage element. Therefore, each data channel is fully aligned with the master clock signal. The clock-data alignment function may be implemented for a 100BASE-T4 receiver.

Abstract: Pre-formatted MAC Control PAUSE frames are generated by a MAC device rather than by a switch. These may be automatically generated and transmitted upon the occurrence of a full or near full condition in the input buffer of the MAC device. The MAC device, upon receipt of a MAC Control PAUSE frame, allows a packet in the process of being transmitted to complete transmission prior to implementing the PAUSE. The MAC device is capable of generating MAC Control frames having any desired opcode. The parameter field associated with the MAC Control frame opcode is programmable. The destination address of the MAC Control frame is programmable. Automatic x-on/x-off is implemented. Flags may be set to enable/disable the IEEE 802.3x pause function in the MAC device and to override basic IEEE 802.3x operation in various ways.

Abstract: An apparatus and method for aligning any number of multiple parallel channels of data signals according to a single clock is provided. The synchronization process is accomplished through the use of a First-In-First-Out (FIFO) principle and individual storage elements implementing the FIFO principle for each received data channel. Each channel's data signals are read into a corresponding storage element, maintained in order, and read out upon the assertion of read signals in synchronization with a designated single clock signal. The apparatus and method preferably uses indications of data ready to be read from a storage element implementing the FIFO principle and the presence of a master clock signal to activate the reading of the data from the corresponding storage element. Therefore, each data channel is fully aligned with the master clock signal. The clock-data alignment function may be implemented for a 100BASE-T4 receiver.

Abstract: In a 100BASE-T4 protocol network, the "carrier.sub.-- status" signal associated with an incoming packet on a PMA of a given port of a Clause 27 repeater is obviated and a direct connection between PMAs and a Clause 27 repeater in the network is eliminated by transmitting synthetic preamble signals over the PMA-Repeater Data Interface to the Clause 27 repeater corresponding to the given port at an early time prior to the time that the actual preamble information of the packet is transmitted over that data interface. Receipt of the synthetic preamble signals causes the repeater to awaken and to repeat the synthetic preamble signals to other ports of the repeater. In turn, the other ports become quiet in anticipation of data to be repeated from the given port to the other ports of the repeater.

Abstract: The present invention allows for the detection and correction of certain error conditions in packet-based data communications systems, including systems utilizing multiple channels or signal pairs, where all channels or signal pairs do not carry a link integrity signal or other repetitive non-data signal. A first aspect of the present invention provides detection and correction for reverse polarity. A second aspect of the present invention provides detection and correction for pair swap. A third aspect of the present invention provides a link integrity function. Detection of reverse polarity, detection of pair swap, and detection of link integrity utilizes the non-data components of received packets, either independently or in conjunction with a link integrity signal or other repetitive non-data signal. Reverse polarity is corrected by inverting the received signals prior to transmission or repetition to subsequent circuitry.

Abstract: The present invention allows for the detection and correction of certain error conditions in packet-based data communications systems, including systems utilizing multiple channels or signal pairs, where all channels or signal pairs do not carry a link integrity signal or other repetitive non-data signal. A first aspect of the present invention provides detection and correction for reverse polarity. A second aspect of the present invention provides detection and correction for pair swap. A third aspect of the present invention provides a link integrity function. Detection of reverse polarity, detection of pair swap, and detection of link integrity by utilizes the non-data components of received packets, either independently or in conjunction with a link integrity signal or other repetitive non-data signal. Reverse polarity is corrected by inverting the received signals prior to transmission or repetition to subsequent circuitry.