Patents by Inventor Eric Thomas Sharp

Eric Thomas Sharp has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5841196
    Abstract: A method of forming a via in a interlevel dielectric of a semiconductor device wherein the via has a fluted sidewall. A semiconductor substrate is provided having a first conductive layer formed thereon. A dielectric layer is then formed on the first conductive layer. A photoresist layer is deposited on a dielectric layer and a contact opening is formed in the photoresist layer to expose a contact region of the dielectric layer. A first etch step is performed to remove portions of the dielectric layer proximal to the contact region to form a first stage of the fluted via. The first stage includes a first sidewall stage extending from an upper surface of the dielectric layer at an angle less than 50.degree.. The first stage of the fluted via exterds a first lateral distance which is greater than a lateral dimension of the contact opening. A second etch step is then performed to further remove portions of the dielectric layer to form a second stage of the fluted via.
    Type: Grant
    Filed: November 14, 1997
    Date of Patent: November 24, 1998
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Subhash Gupta, Robert Flores, Michael Ross Stamm, Eric Thomas Sharp, Erich W. E. Denninger, Pamela G. Dye, Joel Samuel Utz, James K. Kai
  • Patent number: 5746884
    Abstract: A method of forming a via in a interlevel dielectric of a semiconductor device wherein the via has a fluted sidewall. A semiconductor substrate is provided having a first conductive layer formed thereon. A dielectric layer is then formed on the first conductive layer. A photoresist layer is deposited on a dielectric layer and a contact opening is formed in the photoresist layer to expose a contact region of the dielectric layer. A first etch step is performed to remove portions of the dielectric layer proximal to the contact region to form a first stage of the fluted via. The first stage includes a first sidewall stage extending from an upper surface of the dielectric layer at an angle less than 50.degree.. The first stage of the fluted via extends a first lateral distance which is greater than a lateral dimension of the contact opening. A second etch step is then performed to further remove portions of the dielectric layer to form a second stage of the fluted via.
    Type: Grant
    Filed: August 13, 1996
    Date of Patent: May 5, 1998
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Subhash Gupta, Robert Flores, Michael Ross Stamm, Eric Thomas Sharp, Erich W. E. Denninger, Pamela G. Dye, Joel Samuel Utz, James K. Kai