Abstract: Disclosed herein are technologies for forming a plurality of known good die (KGD)-light emitting diode (LED) components into a larger size optically coherent LED chips or devices. This Abstract is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Abstract: Disclosed herein are technologies for forming a plurality of known good die (KGD)-light emitting diode (LED) components into a larger size optically coherent LED chips or devices.

Abstract: Disclosed herein are technologies for forming a plurality of known good die (KGD)-light emitting diode (LED) components into a larger size optically coherent LED chips or devices. This Abstract is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Abstract: Disclosed herein are technologies for forming a plurality of known good die (KGD)—light emitting diode (LED) components into a larger size optically coherent LED chips or devices.

Abstract: Various semiconductor chip packages and methods of making the same are provided. In one aspect, a method of manufacturing is provided that includes providing a substrate that has a first side and a first plurality of passive devices on the first side. A stiffener frame is coupled on the first side. The stiffener frame has first and second spaced apart opposing walls that define a channel in which the first plurality of passive devices is positioned, and a central opening that does not cover a central portion of the first side of the substrate.

Abstract: Various semiconductor chip packages and methods of making the same are provided. In one aspect, a method of manufacturing is provided that includes providing a substrate that has a first side and a first plurality of passive devices on the first side. A stiffener frame is coupled on the first side. The stiffener frame has first and second spaced apart opposing walls that define a channel in which the first plurality of passive devices is positioned, and a central opening that does not cover a central portion of the first side of the substrate.

Abstract: Various semiconductor chip packages and methods of making the same are provided. In one aspect, a method of manufacturing is provided that includes providing a substrate that has a first side and a first plurality of passive devices on the first side. A stiffener frame is coupled on the first side. The stiffener frame has first and second spaced apart opposing walls that define a channel in which the first plurality of passive devices is positioned, and a central opening that does not cover a central portion of the first side of the substrate.

Abstract: Various methods and apparatus for semiconductor packing are disclosed. In one aspect, a method of manufacturing is provided that includes coupling first ends of plural conductor pins to a first surface of a semiconductor chip package substrate. A layer is formed on the first surface that engages and resists lateral movement of the conductor pins while leaving second ends of the conductor pins exposed.

Abstract: Various semiconductor chip packages and methods of making the same are provided. In one aspect, a method of manufacturing is provided that includes providing a substrate that has a first side and a first plurality of passive devices on the first side. A stiffener frame is coupled on the first side. The stiffener frame has first and second spaced apart opposing walls that define a channel in which the first plurality of passive devices is positioned, and a central opening that does not cover a central portion of the first side of the substrate.

Abstract: Various semiconductor chip packages and methods of making the same are provided. In one aspect, a method of manufacturing is provided that includes providing a substrate that has a first side and a first plurality of passive devices in the first side. A polymeric stiffener ring is formed on the first side. The stiffener ring embeds the first plurality of passive devices without covering a central portion of the first surface of the substrate. A semiconductor chip is mounted on the central portion of the first surface of the substrate.

Abstract: Various methods and apparatus for semiconductor packing are disclosed. In one aspect, a method of manufacturing is provided that includes coupling first ends of plural conductor pins to a first surface of a semiconductor chip package substrate. A layer is formed on the first surface that engages and resists lateral movement of the conductor pins while leaving second ends of the conductor pins exposed.

Abstract: Decoupling capacitors and methods of manufacturing the same are provided. In one aspect, a method of manufacturing is provided that includes providing a semiconductor chip and providing a capacitor stack for the semiconductor chip. The capacitor stack includes a first group of terminations and a second group of terminations. A first group of electrodes is included that have terminals coupled to the first group of terminations and a second group of electrodes is included that have terminals coupled to the second group of terminations. At least one electrode of the first group of electrodes has at least one less terminal than the number of terminations in the first group of terminations in order to provide the capacitor stack with a known equivalent series resistance. The capacitor stack is electrically coupled to the semiconductor chip.

Abstract: A method of routing connections of an integrated circuit package having a set of top side conductors and bottom side conductors. The method includes defining at least one distribution layer within the package, and positioning a set of upper vias between the set of top side conductors and the distribution layer. A set of lower vias is positioned between the distribution layer and the set of bottom side conductors that correspond to the set of top side conductors. One or more connections on the distribution layer are routed between the set of upper vias and the set of lower vias. In this manner, the one or more top side conductors are coupled automatically with their respective one or more bottom side conductors. This process may be implemented using one or more computer modules or computer operations.

Abstract: A method for logically connecting at least one of a plurality of top side conductors of an integrated circuit package with at least one of a plurality of bottom side conductors of the integrated circuit package. The method includes drawing a layout of the bottom side conductors, and drawing a layout of the top side conductors. One or more rings of the top side conductors are defined, and one or more rings of the bottom side conductors are defined. One or more signal sets of the top side conductors are defined, each of said signal sets contains at least two or more top side conductors. The user can select a region of top side conductors to be connected with a region of bottom side conductors, and the selected region of top side conductors is automatically connected with the selected region of bottom side conductors while maintaining the signal set relations.

Abstract: A method of routing connections of an integrated circuit package having a set of top side conductors and bottom side conductors. The method includes defining at least one distribution layer within the package, and positioning a set of upper vias between the set of top side conductors and the distribution layer. A set of lower vias is positioned between the distribution layer and the set of bottom side conductors that correspond to the set of top side conductors. One or more connections on the distribution layer are routed between the set of upper vias and the set of lower vias. In this manner, the one or more top side conductors are coupled automatically with their respective one or more bottom side conductors. This process may be implemented using one or more computer modules or computer operations.