Patents by Inventor Eric Van Grunsven

Eric Van Grunsven has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8679963
    Abstract: A chip scale package has a semiconductor die having an array of die bond pads arranged with a bond pad density per unit area, embedded in a molded die support body having a surface supporting an array of conducting contacts, each of the contacts connected by an electrical lead to a corresponding one of the die bond pads.
    Type: Grant
    Filed: June 12, 2013
    Date of Patent: March 25, 2014
    Assignee: NXP B.V.
    Inventors: Jan Gulpen, Tonny Kamphuis, Pieter Hochstenbach, Leo Van Gemert, Eric Van Grunsven, Marc De Samber
  • Publication number: 20130273731
    Abstract: A chip scale package has a semiconductor die having an array of die bond pads arranged with a bond pad density per unit area, embedded in a molded die support body having a surface supporting an array of conducting contacts, each of the contacts connected by an electrical lead to a corresponding one of the die bond pads.
    Type: Application
    Filed: June 12, 2013
    Publication date: October 17, 2013
    Inventors: Jan GULPEN, Tonny KAMPHUIS, Pieter HOCHSTENBACH, Leo VAN GEMERT, Eric Van GRUNSVEN, Marc De SAMBER
  • Patent number: 8482136
    Abstract: A chip scale package has a semiconductor die having an array of die bond pads arranged with a bond pad density per unit area, embedded in a molded die support body having a surface supporting an array of conducting contacts, each of the contacts connected by an electrical lead to a corresponding one of the die bond pads.
    Type: Grant
    Filed: December 29, 2009
    Date of Patent: July 9, 2013
    Assignee: NXP B.V.
    Inventors: Jan Gulpen, Tonny Kamphuis, Pieter Hochstenbach, Leo van Gemert, Eric van Grunsven, Marc de Samber
  • Publication number: 20110156237
    Abstract: A chip scale package has a semiconductor die having an array of die bond pads arranged with a bond pad density per unit area, embedded in a molded die support body having a surface supporting an array of conducting contacts, each of the contacts connected by an electrical lead to a corresponding one of the die bond pads.
    Type: Application
    Filed: December 29, 2009
    Publication date: June 30, 2011
    Applicant: NXP B.V.
    Inventors: Jan Gulpen, Tonny Kamphuis, Pieter Hochstenbach, Leo van Gemert, Eric van Grunsven, Marc de Samber
  • Publication number: 20070052091
    Abstract: The device of the invention comprises a semiconductor element, a first connection element, a first patterned electrically conductive layer and a second patterned electrically conductive layer. The device is further provided with an encapsulation that encapsulates all except the first conductive layer, which is part of the substrate. The device can be suitably made in that the second conductive layer is provided, in pre-patterned form, with a permeable isolating layer as a foil.
    Type: Application
    Filed: December 15, 2003
    Publication date: March 8, 2007
    Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V.
    Inventors: Johannus Weekamp, Marc De Samber, Eric Van Grunsven