Patents by Inventor Eric Virey

Eric Virey has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7919815
    Abstract: Wafer suitable for semiconductor deposition application can be fabricated to have low bow, warp, total thickness variation, taper, and total indicated reading properties. The wafers can be fabricated by cutting a boule to produce rough-cut wafers, lapping the rough-cut wafers, etching the lapped wafers to remove a defect, deformation zone and relieve residual stress, and chemically mechanically polishing the etched wafers to desired finish properties. Etching can be performed by immersion in a heated etching solution comprising sulfuric acid or a mixture of sulfuric and phosphoric acids. A low pH slurry utilized in chemical mechanical polishing of the spinel wafer can comprise ?-Al2O3 and an organic phosphate.
    Type: Grant
    Filed: March 1, 2006
    Date of Patent: April 5, 2011
    Assignee: Saint-Gobain Ceramics & Plastics, Inc.
    Inventors: Brahmanandam Tanikella, Elizabeth Thomas, Frank L. Csillag, Palaniappan Chinnakaruppan, Jadwiga Jaroniec, Eric Virey, Robert A. Rizzuto