Abstract: A method for statistically analyzing structural test information to identify at least one yield loss mechanism includes executing a plurality of instructions on a computer system. The executed instructions cause the computer system to perform the steps of: 1) identifying potential root causes for items of structural test information obtained for a plurality of semiconductor devices; 2) statistically analyzing the items of structural test information to identify at least one non-random device failure signature within the items of structural test information; and 3) identifying from the potential root causes a probable root cause for at least a first of the at least one non-random device failure signature.

Abstract: In one embodiment, a semiconductor test control system includes a computer system having a plurality of hardware resources; a hypervisor installed on the computer system; and a test floor controller installed on the computer system. The hypervisor virtualizes the hardware resources and provides each of at least one virtual appliance with access to a respective virtual set of hardware resources. Each virtual set of hardware resources places its respective virtual appliance in controlling communication with at least a first aspect of a semiconductor test system, thereby enabling the respective virtual appliance to test a respective type of semiconductor device. The test floor controller is in controlling communication with i) at least a second aspect of the semiconductor test system, and ii) each of the at least one virtual appliance.