Abstract: A system includes a seat pan assembly. The seat pan assembly may include a fixed link having a fore end and an aft end. The seat pan assembly may further include an aft driver link having an aft driver link fore end and an aft driver link aft end, wherein the aft driver link fore end is pivotably coupled to the aft end of the fixed link. The seat pan assembly may further include a fore driven link having a fore driven link fore end and a fore driven link aft end, wherein the fore driven link aft end is pivotably coupled to the fore end of the fixed link.

Abstract: A RAM module that can increase the number of times it may be accessed within a single clock cycle. By knowing the processor's clock speed and determining a critical time, a signal optimizer may be constructed. The critical time is the longest interval of time required for a worst-case scenario memory access. A signal optimizer transforms the clock signal into a signal that has a higher frequency than the original clock signal and maintains both its high state and its low state for at least the critical time. By then allowing the RAM module to perform its access and pre-charge during the dips and posts of the optimized clock signal, the RAM module can perform multiple accesses and pre-charges during one clock cycle. The RAM module can be used for direct memory accesses such that the processor does not need to arbitrate access to the memory.

Abstract: A synchronous SRAM chip that can increase the number of times it may be accessed within a single clock cycle. By knowing the processor's clock speed and determining a critical time, a signal optimizer may be constructed. The critical time is the longest interval of time required for a worst-case scenario memory access. A signal optimizer transforms the clock signal into a signal that has a higher frequency than the original clock signal and maintains both its high state and its low state for at least the critical time. By then allowing the synchronous SRAM chip to perform its access and pre-charge during the dips and posts of the optimized clock signal, the synchronous SRAM chip can perform multiple accesses and pre-charges during one clock cycle. The SRAM chip can be used for direct memory accesses such that the processor does not need to arbitrate access to the memory.