Abstract: A self-compensating chucking device may be provided. The chucking device may form a portion of a latching door handle of a door of an infusion pump. The door and a housing of the infusion pump may form a clam-shell clamp that secures infusion tubing to pumping mechanisms of the infusion pump. The latching door handle may include a latching door mechanism that includes a tapered pin. The tapered pin may extend through an outer portion of a door housing, an opening in a handle of the door, and into an opening in an inner portion of the door housing. The opening in the handle of the door may have a tapered inner surface that corresponds to the taper the tapered pin to form the chucking device. The pin may include a groove configured to accept an E-clip that retains the tapered pin within the door housing.

Abstract: Methods for debugging a processor based on executing a randomly created and randomly executed executable on a fabricated processor. The executable may execute via startup firmware. By implementing randomization at multiple levels in the testing of the processor, coupled with highly specific test generation constraint rules, highly focused tests on a micro-architectural feature are implemented while at the same time applying a high degree of random permutation in the way it stresses that specific feature. This allows for the detection and diagnosis of errors and bugs in the processor that elude traditional testing methods. The processor Once the errors and bugs are detected and diagnosed, the processor can then be redesigned to no longer produce the anomalies. By eliminating the errors and bugs in the processor, a processor with improved computational efficiency and reliability can be fabricated.

Abstract: A self-compensating chucking device may be provided. The chucking device may form a portion of a latching door handle of a door of an infusion pump. The door and a housing of the infusion pump may form a clam-shell clamp that secures infusion tubing to pumping mechanisms of the infusion pump. The latching door handle may include a latching door mechanism that includes a tapered pin. The tapered pin may extend through an outer portion of a door housing, an opening in a handle of the door, and into an opening in an inner portion of the door housing. The opening in the handle of the door may have a tapered inner surface that corresponds to the taper of the tapered pin to form the chucking device. The pin may include a groove configured to accept an E-clip that retains the tapered pin within the door housing.

Abstract: Methods for debugging a processor based on executing a randomly created and randomly executed executable on a fabricated processor. The executable may execute via startup firmware. By implementing randomization at multiple levels in the testing of the processor, coupled with highly specific test generation constraint rules, highly focused tests on a micro-architectural feature are implemented while at the same time applying a high degree of random permutation in the way it stresses that specific feature. This allows for the detection and diagnosis of errors and bugs in the processor that elude traditional testing methods. The processor Once the errors and bugs are detected and diagnosed, the processor can then be redesigned to no longer produce the anomalies. By eliminating the errors and bugs in the processor, a processor with improved computational efficiency and reliability can be fabricated.

Abstract: Methods for designing a processor based on executing a randomly created and randomly executed executable on a fabricated processor. By implementing randomization at multiple levels in the testing of the processor, coupled with highly specific test generation constraint rules, highly focused tests on a micro-architectural feature are implemented while at the same time applying a high degree of random permutation in the way it stresses that specific feature. This allows for the detection and diagnosis of errors and bugs in the processor that elude traditional testing methods. Once the errors and bugs are detected and diagnosed, the processor can then be redesigned to no longer produce the anomalies. By eliminating the errors and bugs in the processor, a processor with improved computational efficiency and reliability can be fabricated.

Abstract: Methods for designing a processor based on executing a randomly created and randomly executed executable on a fabricated processor. By implementing randomization at multiple levels in the testing of the processor, coupled with highly specific test generation constraint rules, highly focused tests on a micro-architectural feature are implemented while at the same time applying a high degree of random permutation in the way it stresses that specific feature. This allows for the detection and diagnosis of errors and bugs in the processor that elude traditional testing methods. Once the errors and bugs are detected and diagnosed, the processor can then be redesigned to no longer produce the anomalies. By eliminating the errors and bugs in the processor, a processor with improved computational efficiency and reliability can be fabricated.

Abstract: A connector assembly for a modular medical device is described herein. The connector assembly includes a main body, a printed circuit board, a frame, an elastomeric sealing structure, and a plurality of contacts. The printed circuit is disposed in the main body and has a plurality of electrical contacts. The frame is configured to be attached to the main body and includes a central opening. The elastomeric sealing structure is disposed in the central opening. The plurality of contacts are each sealingly disposed in the elastomeric sealing structure, each arranged in contact with a corresponding one of the electrical contacts on the printed circuit, and each movable upon deformation of the elastomeric sealing structure.

Abstract: A self-compensating chucking device may be provided. The chucking device may form a portion of a latching door handle of a door of an infusion pump. The door and a housing of the infusion pump may form a clam-shell clamp that secures infusion tubing to pumping mechanisms of the infusion pump. The latching door handle may include a latching door mechanism that includes a tapered pin. The tapered pin may extend through an outer portion of a door housing, an opening in a handle of the door, and into an opening in an inner portion of the door housing. The opening in the handle of the door may have a tapered inner surface that corresponds to the taper the tapered pin to form the chucking device. The pin may include a groove configured to accept an E-clip that retains the tapered pin within the door housing.

Abstract: An apparatus for positioning a substrate support within a processing chamber is provided. In one embodiment, an apparatus for positioning a substrate support includes a yoke comprising a curved surface with a first slot formed therethrough, a base comprising a first surface adapted to support the substrate support and a curved second surface, wherein the curved second surface mates with the curved surface of the yoke and a first slot is formed through the curved second surface of the base, and a first threaded member disposed through the first slot in the yoke and the first slot in the base.

Abstract: Apparatus for processing multiple semiconductor wafers, includes a transfer chamber, a first processing chamber mounted in fixed relation to the transfer chamber and having a first wafer-holding platform with a center, a second processing chamber mounted in adjustable relation to the transfer chamber and to the first chamber and having a second wafer-holding platform with a center, and a robot rotatably mounted within the transfer chamber and having first and second wafer-holding arms spaced parallel to each other for inserting a pair of wafers simultaneously into the first and second chambers and for placing the wafers accurately centered over the respective platforms. The spacing of the platform centers is adjusted relative to the spacing of the robot arms such that the wafers are centered and placed with a preselected degree of accuracy onto the respective platforms for efficient processing of the wafers.

Abstract: An apparatus for positioning a substrate support within a processing chamber is provided. In one embodiment, an apparatus for positioning a substrate support includes a gimbal mechanism having radially aligned clamping that substantially prevents movement from a pre-defined plane of a substrate support coupled to the gimbal mechanism during clamping. In another embodiment, an apparatus for positioning a substrate support includes substrate support disposed in a processing chamber. A stem, coupled to the substrate support, extends through the processing chamber and is coupled to a gimbal assembly. The gimbal assembly has a radial clamping mechanism is adapted to adjust a planar orientation of the substrate support about a plurality of axes without exerting rotational moments on the substrate support during clamping. A bearing assembly, having a first carriage block and a second carriage block, is coupled to the gimbal assembly.

Abstract: Apparatus for processing multiple semiconductor wafers, includes a transfer chamber, a first processing chamber mounted in fixed relation to the transfer chamber and having a first wafer-holding platform with a center, a second processing chamber mounted in adjustable relation to the transfer chamber and to the first chamber and having a second wafer-holding platform with a center, and a robot rotatably mounted within the transfer chamber and having first and second wafer-holding arms spaced parallel to each other for inserting a pair of wafers simultaneously into the first and second chambers and for placing the wafers accurately centered over the respective platforms. The spacing of the platform centers is adjusted relative to the spacing of the robot arms such that the wafers are centered and placed with a preselected degree of accuracy onto the respective platforms for efficient processing of the wafers.

Abstract: Disclosed are a system and method for providing fault isolation in a computer system including a central processing unit (“CPU”) capable of issuing a signal to a memory to retrieve a requested instruction from the memory when the CPU is booted. The disclosed invention comprises an interception and substitution circuit, coupled to the CPU, capable of intercepting the signal and providing an alternative diagnostics instruction to the CPU in lieu of the requested instruction, the alternative diagnostics instruction providing an indication of proper functioning of the computer system when executed by the CPU. The circuit allows a user to determine whether the CPU and components proximate the CPU are functioning, even when a fault renders conventional, embedded power-on self-test routines non-functional.

Abstract: A read/writable memory formed in the same semiconductor chip as a microprocessor is employed in testing a plurality of hardware interrupt service routines initiated by corresponding devices (and components of devices) during a power-on, self-test(POST) of a computer system. The POST is set in the read-only memory(ROM) of the computer system. The read/writable memory, which is ordinarily inoperative during the POST, is used for storing a diagnostic interrupt vector table, which has a list of interrupt numbers and corresponding addresses of the respective interrupt routines. This table is normally subject to change because each device and each of its components have different interrupt service routines, requiring different addresses for the same interrupt number. The random access memory(RAM) has not yet been tested in the POST, and is not regarded as reliable for the hardware interrupt testing and therefore the read/writable memory is used for such testing.

Abstract: The invention relates to a method for rotating a source pixel matrix to provide a rotated destination matrix. The method operates on a computer system which includes a processor, a memory and a temporary storage portion. The temporary storage portion includes a plurality of rows where each row includes a plurality of storage locations. The method includes the steps of loading a first set of rows of the temporary storage portion with a lower portion of the source pixel matrix, loading a second set of rows of the temporary storage portion with an upper portion of the source pixel matrix, skewing the source pixel matrix loaded in first and second sets of rows to provide a skewed pixel matrix, alternately rotating selected portions of the skewed pixel matrix stored in selected rows of the first and second sets of rows horizontally and vertically to provide a rotated pixel matrix, and unscrambling the rotated pixel matrix to provide the rotated destination matrix.

Abstract: Disclosed are a circuit and method for dynamically determining cache memory size. The method comprises the steps of (1) writing a replacement data pattern into a first addressable location of a cacheable portion of addressable space, thereby placing the replacement data pattern into a corresponding first addressable location in a cache memory and setting a tag in the first addressable location, (2) accessing an assumed number of remaining addressable locations in the portion of the addressable space thereby setting tags in each of the remaining addressable locations and (3) reading the first addressable location in the cache memory to determine whether the replacement data pattern remains in the first addressable location, the cache memory being of an assumed size if the replacement data pattern is not in the first addressable location in the cache memory. The circuit and method are able to size cache memory without reference to cache size data stored in cache controllers or hardware timers.

Abstract: Disclosed are an apparatus and method for testing a direct memory access ("DMA") controller. The apparatus comprises (1) a virtual control device including a virtual control latch, the virtual control device coupled to a request input of the DMA controller and capable of transmitting a signal to the DMA controller representing a request to transfer data and (2) a virtual input/output ("I/O") device including a virtual I/O latch, an acknowledgement output of the DMA controller coupled to the virtual I/O device, the virtual I/O latch capable of storing the data for use by the DMA controller. In its preferred embodiment, the present invention operates within the confines of IBM-compatible personal computer architecture, allowing DMA controller functionality to be tested directly.

Abstract: Disclosed is a diagnostic procedure for identifying and sizing computer memory, which, in the preferred embodiment of the invention, comprises SIMMs. The procedure comprises the steps of (1) testing a plurality of memory locations in the unit by writing and reading bit patterns to memory locations in succession to determine whether any of the memory locations contains any responding bits and (2) stipulating the unit to be present when a number of the memory locations having any responding bits reaches a predetermined minimum number. The procedure is uniquely designed to detect memory which is not fully functional.

Abstract: Disclosed are a system and method for providing user-invocable, non disk-based diagnostics routines for a personal computer. The method comprises the steps of (1) storing a diagnostics routine capable of performing diagnostic tests on portions of the personal computer in ROM, (2) monitoring a status of a reset button coupled to the personal computer and (3) executing the diagnostics routine if the reset button is pressed twice within a preselected period of time. The disclosed system and method allow a user to control the invocation of a diagnostics routine that needs a minimum of functioning computer hardware to execute.