Patents by Inventor Eric W. Tremble
Eric W. Tremble has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11282806Abstract: The present disclosure relates to semiconductor structures and, more particularly, to partitioned substrates with interconnect bridge structures and methods of manufacture. The structure includes: a plurality of substrates; at least one chip bonded and electrically connected to each of the plurality of substrates; and an interconnect bridge that physically connects the plurality of substrates and electrically connects each of the plurality of chips bonded to each of the plurality of substrates.Type: GrantFiled: October 11, 2019Date of Patent: March 22, 2022Assignee: Marvell Asia Pte, Ltd.Inventors: Wolfgang Sauter, Mark W. Kuemerle, Eric W. Tremble
-
Publication number: 20210111141Abstract: The present disclosure relates to semiconductor structures and, more particularly, to partitioned substrates with interconnect bridge structures and methods of manufacture. The structure includes: a plurality of substrates; at least one chip bonded and electrically connected to each of the plurality of substrates; and an interconnect bridge that physically connects the plurality of substrates and electrically connects each of the plurality of chips bonded to each of the plurality of substrates.Type: ApplicationFiled: October 11, 2019Publication date: April 15, 2021Inventors: Wolfgang SAUTER, Mark W. KUEMERLE, Eric W. TREMBLE
-
Patent number: 10714411Abstract: An IC chip structure including a plurality of IC chips electrically connected to one another in back-end-of-line (BEOL) interconnect layer of the structure is disclosed. The IC structure may include openings in crack-stop structures surrounding the IC chips and a interconnect wire extending between the IC chips through the openings. A packaging structure for utilizing the IC structure where at least one IC chip is inoperable is also disclosed. The structure may include a first bond pad array on a top surface of a packaging substrate including operable bond pads connected to an operable IC chip and structural support bond pads connected to the inoperable IC chip; a second bond pad array on a bottom surface of the substrate including operable bond pads connected to a single IC chip printed circuit board; and an interconnect structure for connecting the operable bond pads of the first and second bond pad arrays.Type: GrantFiled: March 15, 2018Date of Patent: July 14, 2020Assignee: GLOBALFOUNDRIES INC.Inventors: Wolfgang Sauter, Mark W. Kuemerle, Eric W. Tremble, David B. Stone, Nicholas A. Polomoff, Eric S. Parent, Jawahar P. Nayak, Seungman Choi
-
Publication number: 20190363047Abstract: A panel assembly is configured with individual laminates to connect processors in parallel. The individual laminates may be arranged in rows and columns and separated by gaps on adjacent sides. This arrangement forms a placement area comprising a portion of the individual laminates resident in both neighboring rows and neighboring columns. A chip may be disposed on the substrate, the chip spanning the gaps to contact the portion of the individual laminates found in the placement area.Type: ApplicationFiled: May 24, 2018Publication date: November 28, 2019Applicant: GLOBALFOUNDRIES INC.Inventors: Edmund Blackshear, Eric W. Tremble, Wolfgang Sauter, David B. Stone
-
Patent number: 10483233Abstract: A multi-chip module, and method of fabricating the multi-chip module. The multi-chip module includes: a substrate containing multiple wiring layers, each wiring layer having first pads on a top surface of the substrate and second pads on a bottom surface of the substrate, wherein the second pads include split pad and a conventional pad; a first solder ball in direct physical contact with a contiguous bottom surface of the conventional pad and connected to a next level of packaging under the conventional pad, wherein the first solder ball has a first height; and a second solder ball in direct physical contact with first and second sections of the split pad separated by a gap, wherein the second solder ball has a second height that is sufficiently less than the first height such that the second solder ball is not connected to the next level of packaging.Type: GrantFiled: January 26, 2017Date of Patent: November 19, 2019Assignee: International Business Machines CorporationInventors: Anson J. Call, Erwin B. Cohen, Dany Minier, Wolfgang Sauter, David B. Stone, Eric W. Tremble
-
Publication number: 20190287879Abstract: An IC chip structure including a plurality of IC chips electrically connected to one another in back-end-of-line (BEOL) interconnect layer of the structure is disclosed. The IC structure may include openings in crack-stop structures surrounding the IC chips and a interconnect wire extending between the IC chips through the openings. A packaging structure for utilizing the IC structure where at least one IC chip is inoperable is also disclosed. The structure may include a first bond pad array on a top surface of a packaging substrate including operable bond pads connected to an operable IC chip and structural support bond pads connected to the inoperable IC chip; a second bond pad array on a bottom surface of the substrate including operable bond pads connected to a single IC chip printed circuit board; and an interconnect structure for connecting the operable bond pads of the first and second bond pad arrays.Type: ApplicationFiled: March 15, 2018Publication date: September 19, 2019Inventors: Wolfgang Sauter, Mark W. Kuemerle, Eric W. Tremble, David B. Stone, Nicholas A. Polomoff, Eric S. Parent, Jawahar P. Nayak, Seungman Choi
-
Patent number: 9875956Abstract: The present disclosure relates to interface structures and, more particularly, to integrated interface structures with both parallel and serial interfaces and methods of manufacture. The integrated interface structure includes: a substrate; a plurality of serial interface connections integrated on the substrate; and a plurality of parallel interface connections on the integrated substrate and within spaces between sets of the plurality of serial interface connections.Type: GrantFiled: September 26, 2016Date of Patent: January 23, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Wolfgang Sauter, Mark W. Kuemerle, Daniel P. Greenberg, Eric W. Tremble
-
Publication number: 20170141078Abstract: A multi-chip module, and method of fabricating the multi-chip module. The multi-chip module includes: a substrate containing multiple wiring layers, each wiring layer having first pads on a top surface of the substrate and second pads on a bottom surface of the substrate, wherein the second pads include split pad and a conventional pad; a first solder ball in direct physical contact with a contiguous bottom surface of the conventional pad and connected to a next level of packaging under the conventional pad, wherein the first solder ball has a first height; and a second solder ball in direct physical contact with first and second sections of the split pad separated by a gap, wherein the second solder ball has a second height that is sufficiently less than the first height such that the second solder ball is not connected to the next level of packaging.Type: ApplicationFiled: January 26, 2017Publication date: May 18, 2017Inventors: Anson J. Call, Erwin B. Cohen, Dany Minier, Wolfgang Sauter, David B. Stone, Eric W. Tremble
-
Patent number: 9633914Abstract: A multi-chip module and method of fabricating a multi-chip module. The multi-chip module includes: a substrate having a top surface and a bottom surface and containing multiple wiring layers, first pads on the top surface of the substrate and second pads on the bottom surface of the substrate; a first active component attached to a first group of the first pads and a second active component attached to a second group of the first pads; wherein at least one pad of the second pads is a split pad having a first section and a non-contiguous second section separated by a gap, the first section connected by a first wire of the multiple wires to a pad of the first group of first pads and the second section is connected by a second wire of the multiple wires to a pad of the second group of first pads.Type: GrantFiled: September 15, 2015Date of Patent: April 25, 2017Assignee: International Business Machines CorporationInventors: Anson J. Call, Erwin B. Cohen, Dany Minier, Wolfgang Sauter, David B. Stone, Eric W. Tremble
-
Publication number: 20170077000Abstract: A multi-chip module and method of fabricating a multi-chip module. The multi-chip module includes: a substrate having a top surface and a bottom surface and containing multiple wiring layers, first pads on the top surface of the substrate and second pads on the bottom surface of the substrate; a first active component attached to a first group of the first pads and a second active component attached to a second group of the first pads; wherein at least one pad of the second pads is a split pad having a first section and a non-contiguous second section separated by a gap, the first section connected by a first wire of the multiple wires to a pad of the first group of first pads and the second section is connected by a second wire of the multiple wires to a pad of the second group of first pads.Type: ApplicationFiled: September 15, 2015Publication date: March 16, 2017Inventors: Anson J. Call, Erwin B. Cohen, Dany Minier, Wolfgang Sauter, David B. Stone, Eric W. Tremble
-
Patent number: 8438520Abstract: Methods, systems, computer programs, etc., determine the required number of decoupling capacitors, and approximate locations for the decoupling capacitors, for a region of an integrated circuit. Switching elements of the region are entered into a simulation program running on a computerized device. Also, a power distribution model of the region is entered into the simulation program, and a power-supply voltage compression target is entered into the simulation program. These methods, systems, etc., generate an upper number of decoupling capacitors required to satisfy the compression target when all the switching elements concurrently switch. For each switching element, the methods, systems, etc.Type: GrantFiled: August 29, 2011Date of Patent: May 7, 2013Assignee: International Business Machines CorporationInventors: Kurt A. Carlsen, Charles S. Chiu, Umberto Garofano, Ze Gui Pang, Eric W. Tremble, David Toub, Ivan L. Wemple
-
Patent number: 8429590Abstract: In one embodiment, a method for reducing power supply noise within an electronic system that includes an integrated circuit (IC), a package, and a printed circuit board (PCB) connected by a plurality of power delivery networks (PDN) is disclosed. Power supply noise within the system is reduced by defining a voltage compression limit for each PDN of the electronic system; determining a voltage compression for each PDN of the electronic system during a plurality of switching events; comparing the voltage compression of each PDN of the electronic system to the voltage compression limit for each switching event; and in response to the voltage compression of each PDN of the electronic system exceeding the limit, modifying the electronic system to reduce the voltage compression below the limit.Type: GrantFiled: July 18, 2011Date of Patent: April 23, 2013Assignee: International Business Machines CorporationInventors: Timothy W. Budell, Eric W. Tremble
-
Publication number: 20130054202Abstract: Methods, systems, computer programs, etc., determine the required number of decoupling capacitors, and approximate locations for the decoupling capacitors, for a region of an integrated circuit. Switching elements of the region are entered into a simulation program running on a computerized device. Also, a power distribution model of the region is entered into the simulation program, and a power-supply voltage compression target is entered into the simulation program. These methods, systems, etc., generate an upper number of decoupling capacitors required to satisfy the compression target when all the switching elements concurrently switch. For each switching element, the methods, systems, etc.Type: ApplicationFiled: August 29, 2011Publication date: February 28, 2013Applicant: International Business Machines CorporationInventors: Kurt A. Carlsen, Charles S. Chiu, Umberto Garofano, Ze Gui Pang, Eric W. Tremble, David Toub, Ivan L. Wemple
-
Publication number: 20130024831Abstract: In one embodiment, a method for reducing power supply noise within an electronic system that includes an integrated circuit (IC), a package, and a printed circuit board (PCB) connected by a plurality of power delivery networks (PDN) is disclosed. Power supply noise within the system is reduced by defining a voltage compression limit for each PDN of the electronic system; determining a voltage compression for each PDN of the electronic system during a plurality of switching events; comparing the voltage compression of each PDN of the electronic system to the voltage compression limit for each switching event; and in response to the voltage compression of each PDN of the electronic system exceeding the limit, modifying the electronic system to reduce the voltage compression below the limit.Type: ApplicationFiled: July 18, 2011Publication date: January 24, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Timothy W. Budell, Eric W. Tremble
-
Patent number: 7882469Abstract: After finding the shortest conductive signal return-current path for each signal, the invention assesses whether each conductive return-current path is adequate. The method analyzes each shortest conductive signal return-current path and determines if a significant portion of the signal return current flows as displacement current rather than following the conductive current path. A significant displacement current flows when the length of the conductive return-current path that diverges from a signal net is more than a previously defined limit based on the signal transition time. Further, a significant displacement current flows when the overall length of the signal differs from the overall length of the conductive return-current path by more than a previously defined limit based on the signal transition time.Type: GrantFiled: November 27, 2007Date of Patent: February 1, 2011Assignee: International Business Machines CorporationInventors: Timothy W. Budell, David C. Reynolds, Eric W. Tremble
-
Publication number: 20090138836Abstract: After finding the shortest conductive signal return-current path for each signal, the invention assesses whether each conductive return-current path is adequate. The method analyzes each shortest conductive signal return-current path and determines if a significant portion of the signal return current flows as displacement current rather than following the conductive current path. A significant displacement current flows when the length of the conductive return-current path that diverges from a signal net is more than a previously defined limit based on the signal transition time. Further, a significant displacement current flows when the overall length of the signal differs from the overall length of the conductive return-current path by more than a previously defined limit based on the signal transition time.Type: ApplicationFiled: November 27, 2007Publication date: May 28, 2009Inventors: Timothy W. Budell, David C. Reynolds, Eric W. Tremble
-
Publication number: 20090094564Abstract: A method for quickly tracing minimum-length conductive return paths through an electronic structure utilizes a raster based (cellular) memory model comprising individual grids for each layer of the structure. Each grid comprises a reduced resolution N×M cell representation of the conductive structures on that layer. Cellular methodologies are then used to determine, for each signal net, the shortest return path. This information can then be used for various purposes, including determining if the return path is sufficient to ensure adequate signal integrity.Type: ApplicationFiled: October 3, 2007Publication date: April 9, 2009Inventors: Timothy W. Budell, Charles S. Chiu, David C. Reynolds, Eric W. Tremble
-
Patent number: 6945791Abstract: The present invention provides a redistribution package having an upper surface that includes contacts with reduced pitch that correspond, for example, to that of a Controlled Collapse Chip Connection (“C4”) structure formed on a chip, and a lower surface having contacts with increased pitch that correspond, for example, to a printed circuit board employing ball grid array (“BGA”) pads. A series of power, signal and ground conductors extend through the body of the redistribution package and interconnect the circuit board contacts to the chip contacts.Type: GrantFiled: February 10, 2004Date of Patent: September 20, 2005Assignee: International Business Machines CorporationInventors: Timothy W. Budell, Eric W. Tremble, Brian P. Welch