Abstract: Technologies for verifying operations of software components include a device with a processor and a memory coupled with the processor, the memory including instructions that, when executed by the processor cause the processor to obtain design data indicative of a model of interconnected components of a software system. The instructions also cause the processor to obtain test sequence data indicative of rules pertaining to a sequence of messages to be communicated between a target component of the software system and one or more other components of the model defined in the design data. Further, the instructions cause the processor to perform, in a test environment that emulates the model in which the target component is defined, a set of verification operations to determine a response of the target component to one or more messages generated as a function of the test sequence data.

Abstract: The present invention relates to a binary translator for directly translating binary instructions written for a legacy processor to executable binary instructions for a native processor. In accordance with an important aspect of the invention the binary translator is configured as a reconfigurable translator, which enables the binary translator to be used with different legacy processors and/or operating systems and native processors. The binary translators also optimize to take advantage of more efficient native processor instructions and allows portions of the legacy binary code to be disabled and/or new native instructions to be added to the application program without modification of the legacy binary code.

Abstract: A method and system for emulating instructions of legacy microprocessors which execute a compiled high-ordered language, such as C/C++, in which the compiled code is structured such that data and instructions segments are segregated. In order to improve the real-time performance of the system, legacy instructions are directly mapped to equivalent instructions of the host processor where possible. Additional techniques may optionally be employed to further increase the real-time performance of the system. By utilizing the direct mapping of the legacy instructions to host instructions, the emulation system in accordance with the present invention provides increased real-time performance for relatively modern RISC microprocessors.

Abstract: The present invention relates to a binary translator for directly translating binary instructions written for a legacy processor to executable binary instructions for a native processor. In accordance with an important aspect of the invention the binary translator is configured as a reconfigurable translator, which enables the binary translator to be used with different legacy processors and/or operating systems and native processors. The binary translators also optimize to take advantage of more efficient native processor instructions and allows portions of the legacy binary code to be disabled and/or new native instructions to be added to the application program without modification of the legacy binary code.

Abstract: A method and system for emulating instructions of legacy microprocessors which execute a compiled high-ordered language, such as C/C++, in which the compiled code is structured such that data and instructions segments are segregated. In order to improve the real-time performance of the system, legacy instructions are directly mapped to equivalent instructions of the host processor where possible. Additional techniques may optionally be employed to further increase the real-time performance of the system. By utilizing the direct mapping of the legacy instructions to host instructions, the emulation system in accordance with the present invention provides increased real-time performance for relatively modern RISC microprocessors.