Patents by Inventor Eric Woolsey

Eric Woolsey has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10818587
    Abstract: A semiconductor device has a semiconductor die containing a base material having a first surface and a second surface with an image sensor area. A masking layer with varying width openings is disposed over the first surface of the base material. The openings in the masking layer are larger in a center region of the semiconductor die and smaller toward edges of the semiconductor die. A portion of the first surface of the base material is removed by plasma etching to form a first curved surface. A metal layer is formed over the first curved surface of the base material. The semiconductor die is positioned over a substrate with the first curved surface oriented toward the substrate. Pressure and temperature is applied to assert movement of the base material to change orientation of the second surface with the image sensor area into a second curved surface.
    Type: Grant
    Filed: October 1, 2018
    Date of Patent: October 27, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Michael J. Seddon, Francis J. Carney, Eric Woolsey
  • Publication number: 20190035717
    Abstract: A semiconductor device has a semiconductor die containing a base material having a first surface and a second surface with an image sensor area. A masking layer with varying width openings is disposed over the first surface of the base material. The openings in the masking layer are larger in a center region of the semiconductor die and smaller toward edges of the semiconductor die. A portion of the first surface of the base material is removed by plasma etching to form a first curved surface. A metal layer is formed over the first curved surface of the base material. The semiconductor die is positioned over a substrate with the first curved surface oriented toward the substrate. Pressure and temperature is applied to assert movement of the base material to change orientation of the second surface with the image sensor area into a second curved surface.
    Type: Application
    Filed: October 1, 2018
    Publication date: January 31, 2019
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Michael J. SEDDON, Francis J. CARNEY, Eric WOOLSEY
  • Publication number: 20190035718
    Abstract: A semiconductor device has a semiconductor die containing a base material having a first surface and a second surface with an image sensor area. A masking layer with varying width openings is disposed over the first surface of the base material. The openings in the masking layer are larger in a center region of the semiconductor die and smaller toward edges of the semiconductor die. A portion of the first surface of the base material is removed by plasma etching to form a first curved surface. A metal layer is formed over the first curved surface of the base material. The semiconductor die is positioned over a substrate with the first curved surface oriented toward the substrate. Pressure and temperature is applied to assert movement of the base material to change orientation of the second surface with the image sensor area into a second curved surface.
    Type: Application
    Filed: October 1, 2018
    Publication date: January 31, 2019
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Michael J. SEDDON, Francis J. CARNEY, Eric WOOLSEY
  • Patent number: 10115662
    Abstract: A semiconductor device has a semiconductor die containing a base material having a first surface and a second surface with an image sensor area. A masking layer with varying width openings is disposed over the first surface of the base material. The openings in the masking layer are larger in a center region of the semiconductor die and smaller toward edges of the semiconductor die. A portion of the first surface of the base material is removed by plasma etching to form a first curved surface. A metal layer is formed over the first curved surface of the base material. The semiconductor die is positioned over a substrate with the first curved surface oriented toward the substrate. Pressure and temperature is applied to assert movement of the base material to change orientation of the second surface with the image sensor area into a second curved surface.
    Type: Grant
    Filed: July 25, 2016
    Date of Patent: October 30, 2018
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Michael J. Seddon, Francis J. Carney, Eric Woolsey
  • Publication number: 20170084661
    Abstract: A semiconductor device has a semiconductor die containing a base material having a first surface and a second surface with an image sensor area. A masking layer with varying width openings is disposed over the first surface of the base material. The openings in the masking layer are larger in a center region of the semiconductor die and smaller toward edges of the semiconductor die. A portion of the first surface of the base material is removed by plasma etching to form a first curved surface. A metal layer is formed over the first curved surface of the base material. The semiconductor die is positioned over a substrate with the first curved surface oriented toward the substrate. Pressure and temperature is applied to assert movement of the base material to change orientation of the second surface with the image sensor area into a second curved surface.
    Type: Application
    Filed: July 25, 2016
    Publication date: March 23, 2017
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Michael J. SEDDON, Francis J. CARNEY, Eric WOOLSEY
  • Publication number: 20100117231
    Abstract: A wafer level chip scale package (WLCSP) includes a semiconductor device with a plurality of solder bump pads, patterned passivation regions above each of the solder bump pads, a patterned under bump metallization (UBM) region on each of the solder bump pads and the passivation regions, a polyimide region over a portion of the UBM regions and the passivation regions, solder bumps formed on each of the UBM regions.
    Type: Application
    Filed: January 20, 2010
    Publication date: May 13, 2010
    Inventors: Dennis Lang, Sonbol Vaziri, James Kent Naylor, Eric Woolsey, Chung-Lin Wu, Mike Gruenhagen, Neill Thornton
  • Publication number: 20100081257
    Abstract: Semiconductor device processing and methods for dicing a semiconductor wafer into a plurality of individual dies that can have back surface metallization are described. The methods comprise providing a wafer with pre-diced streets in the wafer's front surface, applying a sidewall masking mechanism to the front surface of the wafer so as to substantially fill the pre-diced streets, thinning the back surface of the wafer so as to dice the wafer (e.g., by grinding, etching, or both) and expose a portion of the sidewall masking mechanism from the back surface of the wafer, and applying a material, such as metal, to the back surface of the diced wafer. These methods can prevent the metal from being deposited on die sidewalls and may allow the separation of individual dies without causing the metal to peel from the back surface of one or more adjacent dies. Other embodiments are also described.
    Type: Application
    Filed: November 24, 2009
    Publication date: April 1, 2010
    Inventors: Craig W. Hendricks, Eric Woolsey, Jim Murphy
  • Patent number: 7655539
    Abstract: Semiconductor device processing and methods for dicing a semiconductor wafer into a plurality of individual dies that can have back surface metallization are described. The methods comprise providing a wafer with pre-diced streets in the wafer's front surface, applying a sidewall masking mechanism to the front surface of the wafer so as to substantially fill the pre-diced streets, thinning the back surface of the wafer so as to dice the wafer (e.g., by grinding, etching, or both) and expose a portion of the sidewall masking mechanism from the back surface of the wafer, and applying a material, such as metal, to the back surface of the diced wafer. These methods can prevent the metal from being deposited on die sidewalls and may allow the separation of individual dies without causing the metal to peel from the back surface of one or more adjacent dies. Other embodiments are also described.
    Type: Grant
    Filed: April 16, 2008
    Date of Patent: February 2, 2010
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Craig Hendricks, Eric Woolsey, Jim Murphy
  • Publication number: 20090261388
    Abstract: Semiconductor device processing and methods for dicing a semiconductor wafer into a plurality of individual dies that can have back surface metallization are described. The methods comprise providing a wafer with pre-diced streets in the wafer's front surface, applying a sidewall masking mechanism to the front surface of the wafer so as to substantially fill the pre-diced streets, thinning the back surface of the wafer so as to dice the wafer (e.g., by grinding, etching, or both) and expose a portion of the sidewall masking mechanism from the back surface of the wafer, and applying a material, such as metal, to the back surface of the diced wafer. These methods can prevent the metal from being deposited on die sidewalls and may allow the separation of individual dies without causing the metal to peel from the back surface of one or more adjacent dies. Other embodiments are also described.
    Type: Application
    Filed: April 16, 2008
    Publication date: October 22, 2009
    Inventors: Craig Hendricks, Eric Woolsey, Jim Murphy
  • Publication number: 20080054461
    Abstract: A wafer level chip scale package (WLCSP) includes a packaged semiconductor device with a plurality of solder bump pads, patterned passivation regions above each of the solder bump pads, a patterned under bump metallization (UBM) region on each of the solder bump pads and the passivation regions, a polyimide region over a portion of the UBM regions and the passivation regions, solder bumps formed on each of the UBM regions, and encapsulation material surrounding the semiconductor die except for at least a portion of each of the solder bumps.
    Type: Application
    Filed: August 30, 2007
    Publication date: March 6, 2008
    Inventors: Dennis Lang, Sonbol Vaziri, James Naylor, Eric Woolsey, Chung-Lin Wu, Mike Gruenhagen, Neill Thornton