Patents by Inventor ERICA J. THOMPSON
ERICA J. THOMPSON has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240096896Abstract: Non-planar integrated circuit structures having mitigated source or drain etch from replacement gate process are described. For example, an integrated circuit structure includes a fin or nanowire. A gate stack is over the fin or nanowire. The gate stack includes a gate dielectric and a gate electrode. A first dielectric spacer is along a first side of the gate stack, and a second dielectric spacer is along a second side of the gate stack. The first and second dielectric spacers are over at least a portion of the fin or nanowire. An insulating material is vertically between and in contact with the portion of the fin or nanowire and the first and second dielectric spacers. A first epitaxial source or drain structure is at the first side of the gate stack, and a second epitaxial source or drain structure is at the second side of the gate stack.Type: ApplicationFiled: November 29, 2023Publication date: March 21, 2024Inventors: Jun Sung KANG, Kai Loon CHEONG, Erica J. THOMPSON, Biswajeet GUHA, William HSU, Dax M. CRUM, Tahir GHANI, Bruce BEATTIE
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Publication number: 20240088296Abstract: A nanowire device includes one or more nanowire having a first end portion, a second end portion, and a body portion between the first end portion and the second end portion. A first conductive structure is in contact with the first end portion and a second conductive structure is in contact with the second end portion. The body portion of the nanowire has a first cross-sectional shape and the first end portion has a second cross-sectional shape different from the first cross-sectional shape. Integrated circuits including the nanowire device and a method of cleaning a semiconductor structure are also disclosed.Type: ApplicationFiled: November 20, 2023Publication date: March 14, 2024Applicant: Intel CorporationInventors: Erica J. THOMPSON, Aditya Kasukurti, Jun Sung Kang, Kai Loon Cheong, Biswajeet Guha, William Hsu, Bruce Beattie
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Patent number: 11869973Abstract: A nanowire device includes one or more nanowire having a first end portion, a second end portion, and a body portion between the first end portion and the second end portion. A first conductive structure is in contact with the first end portion and a second conductive structure is in contact with the second end portion. The body portion of the nanowire has a first cross-sectional shape and the first end portion has a second cross-sectional shape different from the first cross-sectional shape. Integrated circuits including the nanowire device and a method of cleaning a semiconductor structure are also disclosed.Type: GrantFiled: June 20, 2018Date of Patent: January 9, 2024Assignee: Intel CorporationInventors: Erica J. Thompson, Aditya Kasukurti, Jun Sung Kang, Kai Loon Cheong, Biswajeet Guha, William Hsu, Bruce Beattie
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Patent number: 11869891Abstract: Non-planar integrated circuit structures having mitigated source or drain etch from replacement gate process are described. For example, an integrated circuit structure includes a fin or nanowire. A gate stack is over the fin or nanowire. The gate stack includes a gate dielectric and a gate electrode. A first dielectric spacer is along a first side of the gate stack, and a second dielectric spacer is along a second side of the gate stack. The first and second dielectric spacers are over at least a portion of the fin or nanowire. An insulating material is vertically between and in contact with the portion of the fin or nanowire and the first and second dielectric spacers. A first epitaxial source or drain structure is at the first side of the gate stack, and a second epitaxial source or drain structure is at the second side of the gate stack.Type: GrantFiled: September 28, 2018Date of Patent: January 9, 2024Assignee: Intel CorporationInventors: Jun Sung Kang, Kai Loon Cheong, Erica J. Thompson, Biswajeet Guha, William Hsu, Dax M. Crum, Tahir Ghani, Bruce Beattie
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Patent number: 11563119Abstract: Disclosed are etchstop regions in fins of semiconductor devices, and related methods. A semiconductor device includes a buried region, a fin on the buried region, and a gate formed at least partially around the fin. At least a portion of the fin that borders the buried region includes an etchstop material. The etchstop material includes a doped semiconductor material that has a slower etch rate than that of an intrinsic form of the semiconductor material. A method of manufacturing a semiconductor device includes forming a gate on a fin, implanting part of the fin with dopants configured to decrease an etch rate of the part of the fin, removing at least part of the fin, and forming an epitaxial semiconductor material on a remaining proximal portion of the fin.Type: GrantFiled: December 27, 2017Date of Patent: January 24, 2023Assignee: Intel CorporationInventors: Cheng-Ying Huang, Willy Rachmady, Gilbert Dewey, Erica J. Thompson, Aaron D. Lilak, Jack T. Kavalieros
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Patent number: 11443983Abstract: An integrated circuit structure comprises a dielectric layer on a substrate. An open structure is in the dielectric layer, and a void-free metal-alloy interconnect is formed in the open structure, wherein the void-free metal-alloy interconnect comprise a metal-alloy comprising a combination of two or more metallic elements excluding any mixing effects of a seed layer or liner deposited in the open structure prior to a metal fill material, and excluding effects of any doping material on the metal fill material.Type: GrantFiled: September 24, 2018Date of Patent: September 13, 2022Assignee: Intel CorporationInventors: Shaestagir Chowdhury, Sirikarn Surawanvijit, Biswadeep Saha, Erica J. Thompson
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Patent number: 10964800Abstract: Semiconductor devices having fin-end stress-inducing features, and methods of fabricating semiconductor devices having fin-end stress-inducing features, are described. In an example, a semiconductor structure includes a semiconductor fin protruding through a trench isolation region above a substrate. The semiconductor fin has a top surface, a first end, a second end, and a pair of sidewalls between the first end and the second end. A gate electrode is over a region of the top surface and laterally adjacent to a region of the pair of sidewalls of the semiconductor fin. The gate electrode is between the first end and the second end of the semiconductor fin. A first dielectric plug is at the first end of the semiconductor fin. A second dielectric plug is at the second end of the semiconductor fin.Type: GrantFiled: December 2, 2016Date of Patent: March 30, 2021Assignee: Intel CorporationInventors: Byron Ho, Michael L. Hattendorf, Jeanne L. Luce, Ebony L. Mays, Erica J. Thompson
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Publication number: 20200279941Abstract: Disclosed are etchstop regions in fins of semiconductor devices, and related methods. A semiconductor device includes a buried region, a fin on the buried region, and a gate formed at least partially around the fin. At least a portion of the fin that borders the buried region includes an etchstop material. The etchstop material includes a doped semiconductor material that has a slower etch rate than that of an intrinsic form of the semiconductor material. A method of manufacturing a semiconductor device includes forming a gate on a fin, implanting part of the fin with dopants configured to decrease an etch rate of the part of the fin, removing at least part of the fin, and forming an epitaxial semiconductor material on a remaining proximal portion of the fin.Type: ApplicationFiled: December 27, 2017Publication date: September 3, 2020Inventors: Cheng-Ying HUANG, Willy RACHMADY, Gilbert DEWEY, Erica J. THOMPSON, Aaron D. LILAK, Jack T. KAVALIEROS
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Publication number: 20200105757Abstract: Non-planar integrated circuit structures having mitigated source or drain etch from replacement gate process are described. For example, an integrated circuit structure includes a fin or nanowire. A gate stack is over the fin or nanowire. The gate stack includes a gate dielectric and a gate electrode. A first dielectric spacer is along a first side of the gate stack, and a second dielectric spacer is along a second side of the gate stack. The first and second dielectric spacers are over at least a portion of the fin or nanowire. An insulating material is vertically between and in contact with the portion of the fin or nanowire and the first and second dielectric spacers. A first epitaxial source or drain structure is at the first side of the gate stack, and a second epitaxial source or drain structure is at the second side of the gate stack.Type: ApplicationFiled: September 28, 2018Publication date: April 2, 2020Inventors: Jun Sung KANG, Kai Loon CHEONG, Erica J. THOMPSON, Biswajeet GUHA, William HSU, Dax M. CRUM, Tahir GHANI, Bruce BEATTIE
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Publication number: 20200098626Abstract: An integrated circuit structure comprises a dielectric layer on a substrate. An open structure is in the dielectric layer, and a void-free metal-alloy interconnect is formed in the open structure, wherein the void-free metal-alloy interconnect comprise a metal-alloy comprising a combination of two or more metallic elements excluding any mixing effects of a seed layer or liner deposited in the open structure prior to a metal fill material, and excluding effects of any doping material on the metal fill material.Type: ApplicationFiled: September 24, 2018Publication date: March 26, 2020Inventors: Shaestagir CHOWDHURY, Sirikarn SURAWANVIJIT, Biswadeep SAHA, Erica J. THOMPSON
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Publication number: 20200058761Abstract: Semiconductor devices having fin-end stress-inducing features, and methods of fabricating semiconductor devices having fin-end stress-inducing features, are described. In an example, a semiconductor structure includes a semiconductor fin protruding through a trench isolation region above a substrate. The semiconductor fin has a top surface, a first end, a second end, and a pair of sidewalls between the first end and the second end. A gate electrode is over a region of the top surface and laterally adjacent to a region of the pair of sidewalls of the semiconductor fin. The gate electrode is between the first end and the second end of the semiconductor fin. A first dielectric plug is at the first end of the semiconductor fin. A second dielectric plug is at the second end of the semiconductor fin.Type: ApplicationFiled: December 2, 2016Publication date: February 20, 2020Inventors: Byron HO, Michael L. HATTENDORF, Jeanne L. LUCE, Ebony L. MAYS, Erica J. THOMPSON
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Publication number: 20190393350Abstract: A nanowire device includes one or more nanowire having a first end portion, a second end portion, and a body portion between the first end portion and the second end portion. A first conductive structure is in contact with the first end portion and a second conductive structure is in contact with the second end portion. The body portion of the nanowire has a first cross-sectional shape and the first end portion has a second cross-sectional shape different from the first cross-sectional shape. Integrated circuits including the nanowire device and a method of cleaning a semiconductor structure are also disclosed.Type: ApplicationFiled: June 20, 2018Publication date: December 26, 2019Applicant: INTEL CORPORATIONInventors: Erica J. Thompson, Aditya Kasukurti, Jun Sung Kang, Kai Loon Cheong, Biswajeet Guha, William Hsu, Bruce Beattie
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Patent number: 9472456Abstract: Methods for selectively etching titanium and titanium nitride are disclosed. In some embodiments the method involve exposing a workpiece to a first solution to remove titanium nitride, exposing the workpiece to a second solution to remove titanium, and exposing the workpiece to a third solution to remove residual titanium nitride, if any. The solutions are formulated such that they may selectively remove titanium and/or titanium nitride, while not etching or not substantially etching certain other materials such as dielectric materials, oxides, and metals other than titanium.Type: GrantFiled: December 24, 2013Date of Patent: October 18, 2016Assignee: Intel CorporationInventors: Erica J. Thompson, Nabil G. Mistkawi, Rohit Grover
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Publication number: 20150179510Abstract: Methods for selectively etching titanium and titanium nitride are disclosed. In some embodiments the method involve exposing a workpiece to a first solution to remove titanium nitride, exposing the workpiece to a second solution to remove titanium, and exposing the workpiece to a third solution to remove residual titanium nitride, if any. The solutions are formulated such that they may selectively remove titanium and/or titanium nitride, while not etching or not substantially etching certain other materials such as dielectric materials, oxides, and metals other than titanium.Type: ApplicationFiled: December 24, 2013Publication date: June 25, 2015Inventors: ERICA J. THOMPSON, NABIL G. MISTKAWI, ROHIT GROVER