Patents by Inventor Erica Stuecheli
Erica Stuecheli has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240104282Abstract: A method, system, and computer program product for bit flip aware latch placement in integrated circuit generation are provided. The method identifies a chip design for an integrated circuit. A set of chip design constraints, associated with the chip design, is identified. A set of checking groups, associated with a plurality of latches to be placed in the chip design, is determined. Based on the set of chip design constraints and the set of checking groups, a placement scheme for the plurality of latches is selected. The method places the plurality of latches within the chip design based on the placement scheme and the set of checking groups.Type: ApplicationFiled: September 22, 2022Publication date: March 28, 2024Inventors: Benjamin Neil Trombley, Chung-Lung K. Shum, Paul G. Villarrubia, K. Paul Muller, Michael Hemsley Wood, Daniel Arthur Gay, Hua Xiang, Karl Evan Smock Anderson, Erica Stuecheli, Michael Alexander Bowen, Randall J. Darden
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Patent number: 11205092Abstract: Methods, systems and computer program products for clustering simulation failures are provided. Aspects include receiving simulation data comprising a plurality of simulation failure files, generating a token for each simulation failure file of the plurality of simulation failure files, determining a token score for each token for each simulation failure file of the plurality simulation failure files, normalizing each token score for each token in the plurality of simulation failure files utilizing a weighting scheme to create a normalized token score for each token, determining a set of groups for the plurality of simulation failure files, and assigning one or more simulation failure files from the plurality of simulation failure files into a group in the set of groups based at least in part on normalized token score.Type: GrantFiled: April 11, 2019Date of Patent: December 21, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Bryan G. Hickerson, John Reysa, Mohamed Baker Alawieh, Brian Kozitza, Erica Stuecheli, Tuhin Mahmud, Divya Joshi
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Publication number: 20200327364Abstract: Methods, systems and computer program products for clustering simulation failures are provided. Aspects include receiving simulation data comprising a plurality of simulation failure files, generating a token for each simulation failure file of the plurality of simulation failure files, determining a token score for each token for each simulation failure file of the plurality simulation failure files, normalizing each token score for each token in the plurality of simulation failure files utilizing a weighting scheme to create a normalized token score for each token, determining a set of groups for the plurality of simulation failure files, and assigning one or more simulation failure files from the plurality of simulation failure files into a group in the set of groups based at least in part on normalized token score.Type: ApplicationFiled: April 11, 2019Publication date: October 15, 2020Inventors: Bryan G. Hickerson, John Reysa, Mohamed Baker Alawieh, Brian Kozitza, Erica Stuecheli, Tuhin Mahmud, Divya Joshi
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Patent number: 10769334Abstract: A method, computer program product, and a fail recognition apparatus are disclosed for debugging one or more simulation fails in processor design verification that in one or more embodiments includes determining whether a prediction model exists; retrieving, in response to determining the prediction model exists, the prediction model; predicting one or more bug labels using the prediction model; determining whether a fix is available for the one or more predicted bug labels; and simulating, in response to determining the fix is available for the one or more predicted bug labels, the fix for the one or more predicted bug labels.Type: GrantFiled: November 16, 2018Date of Patent: September 8, 2020Assignee: International Business Machines CorporationInventors: Bryan G. Hickerson, Mohamed Baker Alawieh, Brian L. Kozitza, John R. Reysa, Erica Stuecheli
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Publication number: 20200159872Abstract: A method, computer program product, and a fail recognition apparatus are disclosed for debugging one or more simulation fails in processor design verification that in one or more embodiments includes determining whether a prediction model exists; retrieving, in response to determining the prediction model exists, the prediction model; predicting one or more bug labels using the prediction model; determining whether a fix is available for the one or more predicted bug labels; and simulating, in response to determining the fix is available for the one or more predicted bug labels, the fix for the one or more predicted bug labels.Type: ApplicationFiled: November 16, 2018Publication date: May 21, 2020Inventors: Bryan G. Hickerson, Mohamed Baker Alawieh, Brian L. Kozitza, John R. Reysa, Erica Stuecheli
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Patent number: 9098653Abstract: A simulation environment verifies processor-sparing functions in a simulated processor core. The simulation environment executes a first simulation for a simulated processor core. During the simulation, the simulation environment creates a simulation model dump file. At a later point in time, the simulation environment executes a second simulation for the simulated processor core. The simulation environment saves the state of the simulated processor core. The simulation environment then replaces the state of the simulated processor core by loading the previously created simulation model dump file. The simulation environment then sets the state of the simulated processor core to execute processor-sparing code and resumes the second simulation.Type: GrantFiled: November 14, 2013Date of Patent: August 4, 2015Assignee: International Business Machines CorporationInventors: Stefan Letz, Joerg Deutschle, Bodo Hoppe, Erica Stuecheli, Brian W. Thompto
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Patent number: 9015025Abstract: A simulation environment verifies processor-sparing functions in a simulated processor core. The simulation environment executes a first simulation for a simulated processor core. During the simulation, the simulation environment creates a simulation model dump file. At a later point in time, the simulation environment executes a second simulation for the simulated processor core. The simulation environment saves the state of the simulated processor core. The simulation environment then replaces the state of the simulated processor core by loading the previously created simulation model dump file. The simulation environment then sets the state of the simulated processor core to execute processor-sparing code and resumes the second simulation.Type: GrantFiled: October 31, 2011Date of Patent: April 21, 2015Assignee: International Business Machines CorporationInventors: Stefan Letz, Joerg Deutschle, Bodo Hoppe, Erica Stuecheli, Brian W. Thompto
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Publication number: 20140074451Abstract: A simulation environment verifies processor-sparing functions in a simulated processor core. The simulation environment executes a first simulation for a simulated processor core. During the simulation, the simulation environment creates a simulation model dump file. At a later point in time, the simulation environment executes a second simulation for the simulated processor core. The simulation environment saves the state of the simulated processor core. The simulation environment then replaces the state of the simulated processor core by loading the previously created simulation model dump file. The simulation environment then sets the state of the simulated processor core to execute processor-sparing code and resumes the second simulation.Type: ApplicationFiled: November 14, 2013Publication date: March 13, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Stefan Letz, Joerg Deutschle, Bodo Hoppe, Erica Stuecheli, Brian W. Thompto
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Publication number: 20130110490Abstract: A simulation environment verifies processor-sparing functions in a simulated processor core. The simulation environment executes a first simulation for a simulated processor core. During the simulation, the simulation environment creates a simulation model dump file. At a later point in time, the simulation environment executes a second simulation for the simulated processor core. The simulation environment saves the state of the simulated processor core. The simulation environment then replaces the state of the simulated processor core by loading the previously created simulation model dump file. The simulation environment then sets the state of the simulated processor core to execute processor-sparing code and resumes the second simulation.Type: ApplicationFiled: October 31, 2011Publication date: May 2, 2013Applicant: International Business Machines CorporationInventors: Stefan Letz, Joerg Deutschle, Bodo Hoppe, Erica Stuecheli, Brian W. Thompto