Patents by Inventor ERICH EWY

ERICH EWY has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11594801
    Abstract: Embodiments of the invention include autonomous vehicles and mm-wave systems for communication between components. In an embodiment the vehicle includes an electronic control unit (ECU). The ECU may include a printed circuit board (PCB) and a CPU die packaged on a CPU packaging substrate. In an embodiment, the CPU packaging substrate is electrically coupled to the PCB. The ECU may also include an external predefined interface electrically coupled to the CPU die. In an embodiment, an active mm-wave interconnect may include a dielectric waveguide, and a first connector coupled to a first end of the dielectric waveguide. In an embodiment, the first connector comprises a first mm-wave engine, and the first connector is electrically coupled to the external predefined interface. Embodiments may also include a second connector coupled to a second end of the dielectric waveguide, wherein the second connector comprises a second mm-wave engine.
    Type: Grant
    Filed: July 1, 2017
    Date of Patent: February 28, 2023
    Assignee: Intel Corporation
    Inventors: Georgios Dogiamis, Sasha Oster, Telesphor Kamgaing, Erich Ewy, Kenneth Shoemaker, Adel Elsherbini, Johanna Swan
  • Patent number: 11486942
    Abstract: Methods and apparatus relating to processor and chipset continuity testing of package interconnect for functional safety applications are described. In an embodiment, voltage divider logic circuitry divides a reference voltage. Controller logic circuitry compares a divided voltage value from a node of the voltage divider logic circuitry and a threshold voltage value. A first end of the voltage divider logic circuitry is coupled to receive the reference voltage and a second end of the voltage divider logic circuitry is coupled to a Non-Critical-To-Function (NCTF) solder ball. The controller logic circuitry generates an error signal in response to a mismatch between the divided voltage value and the threshold voltage value. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: May 31, 2021
    Date of Patent: November 1, 2022
    Assignee: Intel Corporation
    Inventors: Matthew Lee, Benedict C. Ofuonye, Erich Ewy, Jeffrey Willcoxon
  • Patent number: 11476554
    Abstract: Embodiments of the invention include dielectric waveguides and connectors for dielectric waveguides. In an embodiment a dielectric waveguide connector may include an outer ring and one or more posts extending from the outer ring towards the center of the outer ring. In some embodiments, a first dielectric waveguide secured within the dielectric ring by the one or more posts. In another embodiment, an enclosure surrounding electronic components may include an enclosure wall having an interior surface and an exterior surface and a dielectric waveguide embedded within the enclosure wall. In an embodiment, a first end of the dielectric waveguide is substantially coplanar with the interior surface of the enclosure wall and a second end of the dielectric waveguide is substantially coplanar with the exterior surface of the enclosure wall.
    Type: Grant
    Filed: July 1, 2017
    Date of Patent: October 18, 2022
    Assignee: Intel Corporation
    Inventors: Georgios Dogiamis, Sasha Oster, Telesphor Kamgaing, Erich Ewy, Adel Elsherbini, Johanna Swan
  • Publication number: 20210286022
    Abstract: Methods and apparatus relating to processor and chipset continuity testing of package interconnect for functional safety applications are described. In an embodiment, voltage divider logic circuitry divides a reference voltage. Controller logic circuitry compares a divided voltage value from a node of the voltage divider logic circuitry and a threshold voltage value. A first end of the voltage divider logic circuitry is coupled to receive the reference voltage and a second end of the voltage divider logic circuitry is coupled to a Non-Critical-To-Function (NCTF) solder ball. The controller logic circuitry generates an error signal in response to a mismatch between the divided voltage value and the threshold voltage value. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: May 31, 2021
    Publication date: September 16, 2021
    Applicant: Intel Corporation
    Inventors: MATTHEW LEE, BENEDICT C. OFUONYE, ERICH EWY, JEFFREY WILLCOXON
  • Patent number: 11022657
    Abstract: Methods and apparatus relating to processor and chipset continuity testing of package interconnect for functional safety applications are described. In an embodiment, voltage divider logic circuitry divides a reference voltage. Controller logic circuitry compares a divided voltage value from a node of the voltage divider logic circuitry and a threshold voltage value. A first end of the voltage divider logic circuitry is coupled to receive the reference voltage and a second end of the voltage divider logic circuitry is coupled to a Non-Critical-To-Function (NCTF) solder ball. The controller logic circuitry generates an error signal in response to a mismatch between the divided voltage value and the threshold voltage value. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: June 1, 2021
    Assignee: Intel Corporation
    Inventors: Matthew Lee, Benedict C. Ofuonye, Erich Ewy, Jeffrey Willcoxon
  • Publication number: 20200168972
    Abstract: Embodiments of the invention include autonomous vehicles and mm-wave systems for communication between components. In an embodiment the vehicle includes an electronic control unit (ECU). The ECU may include a printed circuit board (PCB) and a CPU die packaged on a CPU packaging substrate. In an embodiment, the CPU packaging substrate is electrically coupled to the PCB. The ECU may also include an external predefined interface electrically coupled to the CPU die. In an embodiment, an active mm-wave interconnect may include a dielectric waveguide, and a first connector coupled to a first end of the dielectric waveguide. In an embodiment, the first connector comprises a first mm-wave engine, and the first connector is electrically coupled to the external predefined interface. Embodiments may also include a second connector coupled to a second end of the dielectric waveguide, wherein the second connector comprises a second mm-wave engine.
    Type: Application
    Filed: July 1, 2017
    Publication date: May 28, 2020
    Inventors: Georgios DOGIAMIS, Sasha OSTER, Telesphor KAMGAING, Erich EWY, Kenneth SHOEMAKER, Adel ELSHERBINI, Johanna SWAN
  • Publication number: 20200076040
    Abstract: Embodiments of the invention include dielectric waveguides and connectors for dielectric waveguides. In an embodiment a dielectric waveguide connector may include an outer ring and one or more posts extending from the outer ring towards the center of the outer ring. In some embodiments, a first dielectric waveguide secured within the dielectric ring by the one or more posts. In another embodiment, an enclosure surrounding electronic components may include an enclosure wall having an interior surface and an exterior surface and a dielectric waveguide embedded within the enclosure wall. In an embodiment, a first end of the dielectric waveguide is substantially coplanar with the interior surface of the enclosure wall and a second end of the dielectric waveguide is substantially coplanar with the exterior surface of the enclosure wall.
    Type: Application
    Filed: July 1, 2017
    Publication date: March 5, 2020
    Inventors: Georgios DOGIAMIS, Sasha OSTER, Telesphor KAMGAING, Erich EWY, Adel ELSHERBINI, Johanna SWAN
  • Publication number: 20190049510
    Abstract: Methods and apparatus relating to processor and chipset continuity testing of package interconnect for functional safety applications are described. In an embodiment, voltage divider logic circuitry divides a reference voltage. Controller logic circuitry compares a divided voltage value from a node of the voltage divider logic circuitry and a threshold voltage value. A first end of the voltage divider logic circuitry is coupled to receive the reference voltage and a second end of the voltage divider logic circuitry is coupled to a Non-Critical-To-Function (NCTF) solder ball. The controller logic circuitry generates an error signal in response to a mismatch between the divided voltage value and the threshold voltage value. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: June 27, 2018
    Publication date: February 14, 2019
    Applicant: Intel Corporation
    Inventors: MATTHEW LEE, BENEDICT C. OFUONYE, ERICH EWY, JEFFREY WILLCOXON