Abstract: A method for applying a sequence of sensing/read reference voltages in a read channel includes (A) setting a read window based on an estimate of a read channel, (B) setting first, second, and third values of a sequence of sensing voltages to values corresponding to different ones of (i) a left-hand limit of the read window, (ii) a right-hand limit of the read window, and (iii) a point central to the read window, (C) determining whether first, second and third reads are successful, and (D) if the first, second and third reads are not successful, setting fourth and fifth values of the sequence of sensing voltages to values corresponding to different ones of (i) a point between the left-hand limit and the point central to the read window and (ii) a point between the right-hand limit and the point central to the read window.

Abstract: An apparatus includes a plurality of memory dies and a controller. The controller may be communicatively coupled to the plurality of memory dies and configured to utilize multiple copies of a root record containing system data during a boot-up process. The multiple copies of the root record are stored using at least two of the plurality of memory dies.

Abstract: An apparatus comprising a memory and a controller. The memory may be configured to process a plurality of read/program operations. The memory may comprise a plurality of memory units each having a size less than a total size of the memory. The controller may be configured to perform a plurality of reads on a victim cell. The controller may be configured to store measured victim information from the plurality of reads on the victim cell. The controller may be configured to perform one or more reads on a plurality of aggressor cells. The controller may be configured to store measured aggressor information from the one or more reads on the plurality of aggressor cells. The controller may be configured to generate inter-cell interference parameters based on the measured victim information and the measured aggressor information. The controller may be configured to mitigate inter-cell interference based on the inter-cell interference parameters.

Abstract: Described embodiments provide a media controller to read data stored in a media. The media controller determines a value for each bit of a shortened codeword from the media. The shortened codeword includes a plurality of non-shortened bits of a full codeword, where the full codeword includes the plurality of non-shortened bits and one or more shortened bits. Shortened bits correspond to bits unused in the shortened codeword. The media controller converts the determined values for each bit of the shortened codeword into a first set of log-likelihood ratio (LLR) values. The full codeword is decoded using the first set of LLR values for the shortened codeword. The media controller dampens one or more LLR values corresponding to non-shortened bits of the codeword to produce a second set of LLR values and decodes the second set of LLR values.

Abstract: An apparatus comprising a memory and a controller. The memory may be configured to process a plurality of read/write operations. The memory comprises a plurality of memory units each having a size less than a total size of the memory. The controller may be configured to perform a first error correction code decoding on the memory units using a plurality of initial log likelihood ratio values. The controller may be configured to count a number of unsatisfied checks if the first error correction code decoding fails. The controller may be configured to generate a plurality of measured log likelihood ratio values if the number of unsatisfied checks is below a threshold. The plurality of measured log likelihood ratio values are (a) based on calculations using decoded bits of the first error correction code decoding, and (b) used to perform a second error correction code decoding on the memory units.

Abstract: An apparatus having a circuit and a decoder is disclosed. The circuit is configured to adjust an initial one of a plurality of reference voltages in a read channel of a memory by shifting the initial reference voltage an amount toward a center of a window and read a codeword from the memory a number of times. The window bounds a sweep of the reference voltages. Each retry of the reads uses a respective reference voltage from a pattern of the reference voltages. The pattern is symmetrically spaced about the initial reference voltage. The pattern fits in the window. The decoder is configured to generate read data by performing an iterative decoding procedure on the codeword based on the reads.

Abstract: An apparatus comprising a memory and a controller. The memory is configured to process a plurality of read/write operations. The memory comprises a plurality of memory modules each having a size less than a total size of the memory. The controller is configured to salvage data stored in a failed page of the memory determined to exceed a maximum number of errors. The controller copies raw data stored in the failed page. The controller identifies locations of a first type of data cells that fail erase identification. The controller identifies locations of a second type of data cells that have program errors. The controller flips data values in the raw data at the locations of the first type of data cells and the locations of the second type of data cells. The controller is configured to perform error correcting code decoding on the raw data having flipped data values. The controller salvages data stored in the failed page.

Abstract: An apparatus having a device and a circuit is disclosed. The device has a plurality of bit-lines and is configured to store a codeword. The circuit is configured to (i) receive the codeword from the device, (ii) generate a syndrome by performing a portion less than all of an iterative decoding procedure on the codeword and (iii) generate a map of defects according to the syndrome. Each of a plurality of bits in the map corresponds to a respective one of the bit-lines.

Abstract: An apparatus having a circuit and an interface to a nonvolatile memory is disclosed. The circuit is configured to (i) read a plurality of bits in a read channel of the nonvolatile memory. The bits are encoded with a polar code. The circuit is also configured to (ii) generate a plurality of probabilities based on a plurality of log likelihood ratio values of the read channel and (iii) decode the bits based on the probabilities.

Abstract: An apparatus includes a controller and an adaptive error correction code decoder. The controller may be configured to read data from and write data to a memory device. The controller may be further configured to write data in a two-step process, which includes (i) after writing data to a least significant bit (LSB) page, checking the data stored in the LSB page using a first strength error correction code (ECC) decoding process and (ii) after writing data to a most significant bit (MSB) page associated with the LSB page, checking the data stored in both the LSB and MSB pages using a second strength error correction code (ECC) decoding process.

Abstract: An apparatus having mapping and interface circuits. The mapping circuit (i) generates a coded item by mapping write unit bits using a modulation or recursion of past-seen bits, and (ii) calculates a particular state to program into a nonvolatile memory cell. The interface circuit programs the cell at the particular state. Two normal cell states are treated as at least four refined states. The particular state is one of the refined states. A mapping to the refined states mitigates programming write misplacement that shifts an analog voltage of the cell from the particular state to an erroneous state. The erroneous state corresponds to a readily observable illegal or atypical write sequence, and results in a modified soft decision from that calculated based on the normal states only. A voltage swing between the particular state and the erroneous state is less than between the normal states.

Abstract: An apparatus having one or more lookup tables and a decoder is disclosed. The lookup tables are configured to store a plurality of sets of values of log likelihood ratios. The decoder is configured to (i) receive a codeword read from a memory, (ii) receive an initial one of the sets from the lookup tables and (iii) generate read data by decoding the codeword based on the values.

Abstract: An apparatus for reading a non-volatile memory includes a tracking module operable to calculate means and variances of voltage level distributions in a non-volatile memory and to calculate at least one reference voltage to be used when reading the non-volatile memory based on the means and variances, a likelihood generator operable to calculate at least one other reference voltage to be used when reading the non-volatile memory, wherein the at least one other reference voltage is based at least in part on a predetermined likelihood value constellation, and to map read patterns from the non-volatile memory to likelihood values, and a read controller operable to read the non-volatile memory using the at least one reference voltage and the at least one other reference voltage to yield the read patterns.

Abstract: A low-density parity-check decoder in a system with multi-level cells identifies zones of reliability where write errors or stuck cells are identifiable. The system uses assumedly successfully decoded pages associated with bits in a cell to identify candidate write errors or stuck cells and erases a corresponding log-likelihood ratio even where such log-likelihood ratio is saturated, thereby breaking a potential trapping set without post-processing.

Abstract: Systems and methods relating generally to solid state memory, and more particularly to systems and methods for recovering data from a solid state memory. An example data processing system includes a first circuit operable to yield a modified soft data set from a data set accessed from a solid state memory device, and a second circuit operable to apply a data decoding algorithm to the modified soft data to yield a decoded output.

Abstract: Methods and apparatus are provided for detection and decoding in flash memories using a correlation of neighboring bits or errors in neighboring bits. Data from a flash memory device is processed by obtaining one or more read values for a plurality of bits in one or more pages of the flash memory device; converting the one or more read values for the plurality of bits to a reliability value, such as a log likelihood ratio (LLR), for a given bit among said plurality of bits based on a probability that a data pattern was written to the plurality of bits given that a particular pattern was read from the plurality of bits; and decoding the given bit in a given page of the one or more pages using the reliability value. The probability may be obtained from one or more transition probability tables, or may be based on one or more reference cells, prior decoded decisions or performance factors.

Abstract: Systems and method relating generally to solid state memory, and more particularly to systems and methods for generated data from a solid state memory. A data processing system includes a solid state memory, a data de-randomizer circuit operable to de-randomize a read data set accessed from the solid state memory device, a soft data generation circuit operable to receive multiple instances of one or more elements the read data set and access a scramble compensating extended look up table using the multiple instances of the element to receive corresponding soft data, and a data decoder circuit operable to apply a soft decoding algorithm to the soft data to yield a decoded output. Each instance of a respective element may be read using a different reference value.

Abstract: An apparatus includes a memory and a controller. The memory includes a plurality of memory devices. Each memory device has a plurality of page types. The plurality of page types are classified based on error rate variations. The controller may be configured to write user data and error-correction data to the memory. The user data and the error-correction data are organized as a super-page. The super-page includes a plurality of sub-pages. The plurality of sub-pages are written across the plurality of memory devices such that the plurality of sub-pages are stored using more than one of the plurality of page types.

Abstract: The present inventions are related to systems and methods for storing data, and more particularly to systems and methods for writing data to a storage device.

Abstract: An apparatus having a circuit and a decoder is disclosed. The circuit is configured to (i) adjust an initial one of a plurality of reference voltages in a read channel of a memory by shifting the initial reference voltage an amount toward a center of a window and (ii) read a codeword from the memory a number of times. The window bounds a sweep of the reference voltages. Each retry of the reads uses a respective reference voltage from a pattern of the reference voltages. The pattern is symmetrically spaced about the initial reference voltage. The pattern fits in the window. The decoder is configured to generate read data by performing an iterative decoding procedure on the codeword based on the reads.